Defense Event

Area- and Energy-Efficient Modular Circuit Architecture for Parallel Neural Recording Microsystems

Sung-Yun Park

PhD Candidate
Friday, May 06, 2016
09:00am - 11:00am
1005 EECS

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About the Event

In the past few decades, there has been significant progress in the development of neural recording systems as with fast advances in electronics and micro-electro-mechanical-systems (MEMS) technologies. The number of simultaneous recorded neurons has been doubled at every 7 years, following a trend similar to Moore’s law, although much slower. Even though various clinical systems such as neural prosthetics have taken advantage of such rapid growth in technologies, comprehensive neuroscience research still has unmet need of high-quality and parallel monitoring over a large number of neurons within a small volume of target brain areas for in-depth understanding of neuronal connectivity, circuits and activities. This research focuses on developing a system architecture and associated electronic circuit implementation for a modular, massive-parallel neural recording system capable of recording 1,024 channels simultaneously as a next-generation neuroscience research tool. Three interdependent prototypes have been developed to address major challenges in realization of massive-parallel neural recording microsystems: a 128-channel Δ-ΔΣ analog front-end (AFE) using the spectrum shaping technique, an on-chip mixed signal neural signal compressor and an on-chip dc-to-dc converter. The fabricated AFE can be extended to a 1,024-channel parallel recording system via hybrid assembly with the customized 3-dimension platform consisting of multi-shank probes, interposers, and silicon-encapsulation. The implemented system has achieved 4.84 fJ/C−s·mm2 figure of merit that is the smallest the area-energy product among the state-of-the-art multichannel neural recording systems.

Additional Information

Sponsor(s): ECE

Faculty Sponsor: Chair: Euisik Yoon

Open to: Public