ECE
ECE
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Defense Event

Low Power Techniques for Analog Building Blocks of the Ultra Low Power System

Yen-Po Chen


PhD Candidate
 
Tuesday, August 02, 2016
1:00pm - 3:00pm
1008 EECS

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About the Event

By the Moore’s law of technology scaling and Bell’s Law of prediction on the next generation small form factor computer class, the mm-scale sensor nodes are widely considered to be the next generation of computer class. With the limited size of the sensor nodes, the capacity of the battery is extremely small or can be even battery less. Therefore, the ultra-low power design technique is critical for those sensor nodes to sustain reasonable lifetime. Among all the building blocks of those sensor nodes, power consumption of analog parts benefits least from the technology scaling compared to the digital and the memory counterparts and widely becomes the dominant part of the power consumption of the system. Therefore, this thesis is focus on bringing down the power consumption of the analog circuits. The following techniques are described in this thesis with the order: First, an advanced sample and hold technique for bandgap voltage reference to duty-cycled the blocks and reducing the power consumption is presented. Second, a technique for reducing leakage power of the ESD clamp circuits by addressing both GIDL leakage and subthreshold leakage is presented. Third, a new trade-off technique between noise and bandwidth for the amplifier design is established in an ECG amplifier example. Fourth, an ECG sensor system shows the possibility to bring down the analog power consumption and balance the power consumption between analog and digital blocks by co-design with digital algorithm.

Additional Information

Sponsor(s): ECE

Faculty Sponsor: Chair: Dennis Sylvester

Open to: Public