About the Event
From the smartphone to the data center, the world today demands computers that are both responsive and energy-efficient. While Moore’s law has continued to provide exponentially more transistors, increased power density has made it difficult to use all the transistors simultaneously. This limitation has forced architects to seek alternative designs that trade small increases in area for large gains in energy efficiency.
Heterogeneous Multicore Systems (HMs) — comprising multiple cores with varying performance and energy characteristics — have emerged as a promising approach for improving energy efficiency while continuing to deliver high performance. HMs reduce energy consumption by identifying application phases and migrating execution to the most efficient core that meets performance requirements. However, migration requires tens of thousands of cycles to complete, limiting their opportunities to coarse-graphed phases of hundreds of millions of instructions, reducing their potential to exploit energy-efficient cores. Additionally, the most efficient core is determined by sampling on all cores, potentially missing short-duration phase behavior that could be exploited to increase energy efficiency.
To counter these limitations, this thesis proposes bringing heterogeneity into the core itself. We propose Composite Cores, an architecture that pairs an high-performance Out-of-Order(OoO) backend and an energy-efficient In-Order (InO) backend that together achieve high performance and energy efficiency. By sharing architectural state between the backends, the migration overhead can be significantly reduced, enabling fine-grained migrationand increasing the opportunities to utilize the InO backend without sacrificing performance. An intelligent controller migrates the application between backends to maximize energy efficiency while constraining performance loss to a configurable bound. Together these innovations enable Composite Cores to save more energy without sacrificing performance.
This thesis provides a design of the Composite Core architecture, as well as offer a novel hardware migration control mechanism. We demonstrate the improved energy saving benefits of this design over traditional HM architectures. We further show that this design offers superior energy savings potential than it’s chief competitor, Dynamic Voltage and Frequency Scaling. Finally, this thesis explores the limits of fine-grained heterogeneity by extending the Composite Core architecture further, revealing additional energy-savings potential.