CMOS Sensors for Time-Resolved Active Imaging
Tuesday, December 20, 2016|
08:00am - 10:00am
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About the Event
In the past decade, time-resolved imaging such as fluorescence lifetime or time-of-flight depth profile has drawn attention in biomedical and industrial applications. Many studies have shown its potential and effectiveness in cancer detection, tissue diagnoses, gesture/motion sensing and geometry sensing. However, time-resolved image sensors are not widely used in the real world due to high system cost, performance degradation by ambient light, and slow imaging speed. To address these problems, this research focuses on an implementation of low-cost time-resolved imaging systems with high frame-rate, high accuracy and suppression of background light. Three image sensing schemes are proposed. First, a single-shot high-speed fluorescence lifetime imager is implemented using two-tap pixels that oversample the fluorescence in sub-nanosecond resolution and calculates the center-of-mass of the signal. The pixel-level calculation compresses the oversampled data, the proposed pixel architecture can achieve high accuracy as well as high speed compared to conventional approaches. Second, a portable 3-D camera has been implemented that can work under various lighting conditions. Column-level background light suppression circuits are integrated in a small pixel (5.9) and can suppress the background light over 100 klx under outdoor sunlight. The spatiotemporal resolution of the sensor can be adaptively reconfigured by pixel-binning and superresolution to provide the optimum performance under various lighting conditions. Finally, a multi-tap pixel with a compressive ADC scheme for low-light imaging is implemented. The proposed pixel provides multi-bit quantization of signals in both time- and intensity-domains for better accuracy even under low-light conditions. The data from the pixel array are compressed by the proposed ADC to reduce data-rate. The compression ratio of the ADC is adjusted to maximize the overall imaging speed by balancing the speed of ADC and the throughput of I/O ports.
Faculty Sponsor: Prof. Euisik Yoon
Open to: Public