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Defense Event

Architecting Persistent Memory Systems

Aasheesh Kolli


 
Friday, March 31, 2017
10:00am - 12:00pm
3725 Beyster Bldg.

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About the Event

Persistent Memory (PM) technologies (also known as Non-Volatile RAM, e.g., Intel’s 3D XPoint) offer the exciting possibility of disk-like durability with the performance of main memory. Persistent memory systems provide applications with direct access to storage media via processor load and store instructions rather than having to rely on performance sapping software intermediaries like the operating system, aiding the development of high-performance, recoverable software. For example, I envision storage software that provides the safety and correctness of a conventional database management system like PostgreSQL and the performance of an in-memory store like Redis. However, today’s computing systems have been optimized for block storage devices and cannot fully exploit the benefits of PMs. Designing efficient systems for this new storage paradigm requires a careful rethink of computer architectures, programming interfaces, and application software. While maintaining recoverable data structures in main memory is the central appeal of persistent memories, current systems do not provide efficient mechanisms (if any) to do so. Ensuring the recoverability of these data structures requires constraining the order of PM writes, whereas current architectures are designed to reorder memory accesses, transparent to the programmer, for performance. Recently, programming interfaces, called persistency models, that will allow programmers to express the required order of PM writes have been proposed. This thesis proposes efficient hardware implementations to enforce the PM write order prescribed by persistency models, proposes how to enhance hihg-level programming languages (like C++) to provide persistency guarantees, and shows how to tailor software for these new programming interfaces.

Additional Information

Sponsor(s): Thomas F. Wenisch

Open to: Public