Defense Event

Efficient Continuous-Time Sigma-Delta Converters for High Frequency Applications

Mehmet Dayanik

Monday, May 08, 2017
2:00pm - 3:30pm
3316 EECS

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About the Event

Abstract: Over the years Continuous-Time (CT) Sigma-Delta (ΣΔ) modulators have received a lot of attention due to their ability to efficiently digitize a variety of signals, and suitability for many different applications. Because of their tolerance to component mismatch, the easy to drive input structure, as well as intrinsic anti-aliasing filtering and noise shaping abilities, CTΣΔ modulators have become one of the most popular data-converter type for high dynamic range and moderate/wide bandwidth. This trend is the result of faster CMOS technologies along with design innovations such as better architectures and faster amplifiers. The goal of this research is to use the noise shaping benefits of CTΣΔ modulators for different wireless applications, while achieving high resolution and/or wide bandwidth. The first part of this research presents a noise shaping time-to- digital converter (TDC), based on a CTΣΔ modulator. This is intended to reduce the in-band phase noise of a high frequency digital phase lock loop (PLL) without reducing its loop bandwidth. To prove the effectiveness of the proposed TDC, two fractional-N digital PLL are designed as a signal sources for a 240GHz FMCW radar system. The second part focuses on high-speed (GS/s) CTΣΔ modulators for wireless communication, and introduces a time-interleaved reference data weighted averaging (TI-RDWA) architecture suitable for GS/s CTΣΔ modulators. This architecture shapes the digital-to- analog converter (DAC) mismatch effects in a CTΣΔ modulator at GS/s operating speeds allowing us to use smaller DAC unit sizes to reduce area and power consumption for the same bandwidth.

Additional Information

Sponsor(s): Professor Michael P. Flynn

Faculty Sponsor: Professor Michael P. Flynn

Open to: Public