MICL Seminar

Continuous-time Pipeline ADC

Hajime Shibata

Design Engineer
Analog Devices
Wednesday, June 28, 2017
11:30am - 12:30pm
1012 EECS

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About the Event

An oversampled continuous-time pipeline ADC clocked at 9 GHz achieving 1.125 GHz bandwidth and –164 dBFS/Hz average small-signal noise density is discussed. In contrast to traditional discrete-time pipeline ADCs, the system processes the signals in continuous-time form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved discretetime pipeline ADCs since continuous-time signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28 nm CMOS process technology and consumes 2.3 W.


Hajime Shibata received BE and ME degrees in electrical engineering from the University of Electro-Communications, Tokyo, Japan, in 1997 and 1999, respectively, and the Dr. Eng. Degree from Tokyo Institute of Technology in 2002. Since 2002, he has been with Analog Devices, where he is working on continuous-time ΔΣ and continuous-time pipeline analog-to-digital converter designs.

Additional Information

Contact: Fran Doman

Phone: 7346153499


Sponsor(s): MICL

Faculty Sponsor: Mike Flynn

Open to: Public