Electrical Engineering and Computer Science


Defense Event

Improve the Usability of Polar Codes: Code Construction, Performance Enhancement and Configurable Hardware

Shuanghong Sun


 
Monday, October 02, 2017
1:00pm - 3:00pm
3316 EECS

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About the Event

Abstract: Error-correcting codes (ECC) have been widely used in modern communication systems to dramatically reduce the signal-to-noise ratio for a given bit error rate. Newly invented polar codes have attracted much interest because of their capacity-achieving potential, efficient codec implementation, and flexible design space. This dissertation is aimed at improving the usability of polar codes by providing a practical code design method, performance improvement approaches, and a configurable hardware design. Extremely low error rates being desired in ECC, FPGA is used to prototype polar decoders to catch rare-case errors for analysis. The FPGA platform achieves significant speedup in large-scale emulations. The frozen set selection determines the error-correcting performance. A simulation-based selection method is developed to rank the bit reliability. The resulting construction is channel adaptive and exhibits significant coding gain. To further improve the coding, the error mechanisms are studied. CRC concatenation detects errors, and post-processing algorithms targeting at distinct error symptoms mitigate the vast majority of them. The regularity of the belief-propagation decoder structure enables many architecture choices, where area, energy, power, throughput and latency can be traded off to reach the optimal design points for practical use cases. For dynamic wireless channels, multiple codes of different lengths and rates are needed to fit varying conditions. A length- and rate-configurable polar decoder ASIC is demonstrated as a universal decoder.

Additional Information

Sponsor(s): Zhengya Zhang

Open to: Public