A CMOS Digital Beamforming Receiver
Monday, September 17, 2018|
3:00pm - 5:00pm
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About the Event
Abstract: As the demand for high speed communication is increasing, 5G wireless is aiming to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming is more accurate, provides multiple simultaneous beams without an SNR penalty, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, beam squinting errors, and ADC non-linearity. First, we address the power and area challenge by combining Interleaved Bit-Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting issue. Third, we present a new current-steering DAC architecture that improves ADC linearity. To summarize, a prototype 16-element, 4-independent beam, 1 GHz center frequency, 100 MHz bandwidth prototype true time delay digital beamformer achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512. The measured beam patterns are near-ideal for both conventional and adaptive beamforming. Despite the high performance, the prototype occupies only 0.29 mm2 and consumes 453 mW.
Sponsor(s): Professor Michael P. Flynn
Open to: Public