EECS
EECS


Defense Event

Analysis and Minimization of Leakage Current

Dongwoo Lee


 
Thursday, June 02, 2005
10:30am - 12:30pm
1005 EECS

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About the Event

Among several metrics for system performance, power consumption has become a major criterion. As voltage and process are scaled down, leakage power has become more significant. Aggressive scaling of operating voltage and process requires the reduction of threshold voltage (Vt) and gate oxide thickness (Tox) for good circuit performance. These reduced Vt and Tox result in a dramatic increase in subthreshold leakage current (Isub) and gate tunneling leakage current (Igate). In addition to standby mode, leakage power during runtime mode needs to be considered in high performance designs. In our research, we developed a new circuit level estimation method for Igate. The interaction between Isub and Igate is considered in this analysis, as is the impact of Igate on circuit behavior. Based on this analysis, we propose a new Igate minimization technique through state assignment and pin reordering. Because Igate depends on the position of conduction devices, pin reordering results in the substantial reduction of Igate. In addition, we proposed a new approach for leakage current minimization including both Isub and Igate. Our proposed method combines the input state dependence of leakage current and dual-Vt / dual-Tox technology. The simultaneous state, Vt and Tox assignment approach uses the basic observation that with a specific input state only some of transistors which are responsible for Isub or Igate need to be assigned to high-Vt or thick-Tox under delay constraint. This allows for a significant improvement in leakage-delay trade-off. Heuristics for the proposed approaches achieve 5X (for Isub only) and 6X (for both Isub and Igate) leakage reduction over traditional methods.

Additional Information

Contact: Bert Wachsman

Phone: 763-4921

Email: bertw@eecs.umich.edu

Sponsor(s): ACAL

Open to: Public