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Verification, Testing, and Physical Design

CSE includes one of the largest and broadest CAD and VLSI research programs in the nation. Research efforts span VLSI design, place and route solutions, logic design, testing, and verification and validation. Our faculty have made seminal contributions in the areas of timing analysis and optimization, formal verification, reliable design, automatic test generation, and low-power design. The group has an exceptional publication record, including numerous best paper awards at the most prestigious conferences and journals in the field. In physical design alone, our research addresses challenges in the specific areas of circuit partitioning, automatic floorplanning, module and transistor placement, physical synthesis, routing and design for manufacturability.

We are studying methodologies and algorithms that promise to improve the performance, power dissipation and cost of next-generation microprocessors, ASICs, systems-on-chip, and other integrated circuits. Our research projects often combine expertise in computer engineering, software development, algorithms, and optimization.

CSE Faculty

Hayes, John P.
Sakallah, Karem A.

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