Electrical Engineering and Computer Science

CSE Technical Reports Sorted by Technical Report Number

TR Number Title Authors Date Pages

CSE-TR-152-93 Hardware Support for Hiding Cache Latency Golden and Mudge Feb, 93 22

CSE-TR-153-93 A Single Symbolic Algorithm for Incremental Concept Acquisition Miller and Laird Jan, 93 7

CSE-TR-154-93 Real-Time Fault-Tolerant Communication in Computer Networks Zheng Feb, 93 102

CSE-TR-155-93 MDARTS: A Multiprocessor Database Architecture for Real-Time Systems Lortz and Shin Mar, 93 19

CSE-TR-157-93 Modeling Concept Acquisition in the Context of a Unified THeory of Cognition Miller Jun, 93 71

CSE-TR-159-93 Analysis of Memory Latency Factors and their Impact on KSR1 MPP Performance Kahhaleh Apr, 93 17

CSE-TR-160-93 Identification of Critical paths in Circuit with Level-Sensitive Latches Burks Sakallah and Mudge Apr, 93 37

CSE-TR-161-93 Surface Fitting for Industrial Applications Schunck Rogers and Sinha Apr, 93 29

CSE-TR-162-93 The Evolving Algebra Semantics of COBOL Vale Apr, 93 29

CSE-TR-163-93 An Information Model for Genome Map Representation and Assembly Lee Rundensteiner Thomas and Lafortune May, 93 25

CSE-TR-164-93 Modeling and Approaching the Deliverable Performance Capability of the KSR1 Processor Azeem Jun, 93 41

CSE-TR-165-93 First-Order Logic Models for Real-Time Discrete-Event Systems Naylor May, 93 45

CSE-TR-166-93 Min-Max Linear Programming Burks and Sakallah Aug, 93 16

CSE-TR-167-93 A Scalable Board-Level-Timing Verification Methodology Daga and Birmingham Aug, 93 16

CSE-TR-168-93 VITCh: A Methodology for the Timing Verification of Board-Level Circuits Daga and Birmingham Aug, 93 12

CSE-TR-169-93 Cyclic Job Shop Scheduling Using Collision Vectors Chaar and Davidson Aug, 93 62

CSE-TR-170-93 A Universal RPC Toolkit Huang and Ravishankar Aug, 93 24

CSE-TR-171-93 Cicero: A Protocol Construction Language Huang and Ravishankar Aug, 93 42

CSE-TR-172-93 Task Allocation and Redistribution in Distributed Real-Time Systems Hou Aug, 93 222

CSE-TR-173-93 Multi-Configuration Simulation Algorithms for the Evaluation of Computer Architecture Designs Sugumar and Abraham Aug, 93 143

CSE-TR-174-93 Automated Design for Concurrent Engineering Darr and Birmingham Sep, 93 20

CSE-TR-175-93 CIRCA: The Coopeartive Intelligent Real-Time Control Architecture Musliner Sep, 93 170

CSE-TR-176-93 Semaphore Queue Priority Assignment for Real-Time Multiprocessor Synchronization Lortz and Shin Sep, 93 23

CSE-TR-177-93 Tailoring Recursion for Complexity Gradel and Gurevich Sep, 93 19

CSE-TR-178-93 Search-Space Pruning Heuristics for Path Sensitization in Test Pattern Generation Silva and Sakallah Oct, 93 17
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay-fault testing. Path sensitization can be posed as a search, in the n-dimensional Boolean space, for a consistent assignment of logic values to the circuit nodes which also satisfies a given condition. While the conditions for path sensitization are different for different applications, the search mechanism need not be. In this paper we propose and demonstrate the effectiveness of several new deterministic techniques for search-space pruning for test pattern generation. These techniques are based on a dynamic analysis of the search process and can be viewed as extensions of methods that were introduced in FAN and SOCRATES. In particular, we present linear-time algorithms for dynamically identifying unique sensitization points and for dynamically maintaining reduced head line sets. In addition, we present two powerful mechanisms that drastically reduce the number of backtracks: failure-driven assertions and dependency-directed backtracking. Both mechanisms can be viewed as a form of learning while searching and have analogs in other application domains. These search pruning methods have been implemented in a generic path sensitization engine called LEAP. A test pattern generator, TG-LEAP, that uses this engine was also developed. We present experimental results that compare the effectiveness of our proposed search pruning strategies to those of PODEM, FAN, and SOCRATES. In particular, we show that LEAP is very efficient in identifying redundant faults and in generating tests for difficult faults.

CSE-TR-179-93 The Minimization and Decomposition of Interface State Machines Daga and Birmingham Oct, 93 14

CSE-TR-180-93 SPIDER: Flexible and Efficient Communication Support for Point-to-Point Distributed Systems Dolter Daniel Mehra Rexford Feng and Shin Oct, 93 14

CSE-TR-181-93 Striping in a RAID Level 5 Disk Array Chen and Lee Oct, 93 15

CSE-TR-182-93 Two-Level Adaptive Branch Prediction and Instruction Fetch Mechanisms for High Performance Superscalar Processors Yeh Oct, 93 101

CSE-TR-183-93 Aggressive Execution Engines for Surpassing Single Basic Block Execution Butler Oct, 93 95

CSE-TR-184-93 Optimal Allocation of On-Chip Memory for Multiple-API Operating Systems Nagle Uhlig Mudge and Sechrest Nov, 93 22

CSE-TR-185-93 Kernel-Based Memory Simulation Nagle Uhlig Mudge and Sechrest Nov, 93 21

CSE-TR-190-93 The Semantics of the C++ Programming Language Wallace Nov, 93 35

CSE-TR-191-93 Implementation Experience with Building an Object-Oriented View Management System Kuno and Rundensteiner Aug, 93 18

CSE-TR-192-93 DOCTOR: An IntegrateD SOftware Fault InjeCTiOn EnviRonment Han Rosenberg and Shin Dec, 93 27

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