CSE Technical Reports Sorted by Technical Report Number
| TR Number |
Title |
Authors |
Date |
Pages |
| Rapid advances in processor performance have shifted the performance bottleneck to I/O systems. The relatively slow rate of improvement in I/O
is due in part to a lack of quantitative performance analysis of software
and hardware alternatives. Using a new self-scaling I/O benchmark, we
provide such an evaluation for 11 hardware configurations using 9
variations of the Unix operating system. In contrast to processor
performance comparisons, where factors of 2 are considered large, we find
differences of factors of 10 to 100 in I/O systems. The principal
performance culprits are the policies of different Unix operating
systems; some policies on writes to the file cache will cause processors
to run at magnetic disk speeds instead of at main memory speeds. These
results suggest a greater emphasis be placed on I/O performance when
making operating system policy decisions.
|
| Ravel-XL is a single-board hardware accelerator for gate-level digital logic simulation. It uses a standard levelized-code approach to statically
schedule gate evaluations. However, unlike previous approaches based on
levelized-code scheduling, it is not limited to zero- or unit-delay gate
models and can provide timing accuracy comparable to that obtained from
event-driven methods. We review the synchronous waveform algebra that
forms the basis of the Ravel-XL simulation algorithm, present an
architecture for its hardware realization, and describe an implementation
of this architecture as a single VLSI chip. The chip has about 900,000
transistors on a die that is approximately 1.4cm^2, requires a 256-pin
package and is designed to run at 33MHz. A Ravel-XL board consisting of the
processor chip and local instruction and data memory can simulate up to one
billion gates at a rate of approximately 6.6 million gate evaluations per
second. To better appreciate the tradeoffs made in designing Ravel-XL, we
compare its capabilities to those of other commercial and research software
simulators and hardware accelerators.
|
Technical Reports Page
|
|
