CSE Technical Reports Sorted by Technical Report Number

TR Number Title Authors Date Pages

CSE-TR-276-96 Distributed Object Replication Support for Collaborative Systems Wu and Prakash Jan, 96 18

CSE-TR-277-96 Characterizing Shared Memory and Communication Performance: A Case Study of the Convex SPP-10000 Abandah and Davidson Jan, 96 16

CSE-TR-278-96 Using Simulation and Performance Improvement Knowledge for Redesigning Business Processes Jaeger and Prakash Jan, 96 32

CSE-TR-279-96 Getting More Information into File Names McClennen and Sechrest Jan, 96 12

CSE-TR-280-96 Design and Evaluation of a QoS-Sensitive Communication Subsystem Architecture Mehra Indiresan and Shin Jan, 96 22

CSE-TR-281-96 Resource Management for Real-Time Communication: Making Theory Meet Practice Mehra Indiresan and Shin Jan, 96 19

CSE-TR-282-96 Limits to Branch Prediction Mudge Chen and Coffey Jan, 96 16

CSE-TR-283-96 Correlation and Aliasing in Dynamic Branch Predictors - Full Simulation Results Sechrest CC Lee and Mudge Feb, 96 107

CSE-TR-284-96 Tool Coordination and Media Integration on Asynchronously-Shared Computer-Supported Workspaces Manohar and Prakash Feb, 96 24

CSE-TR-285-96 Faster Static Timing Analysis via Bus Compression VanCampenhout and Mudge Feb, 96 6

CSE-TR-286-96 The Rio File Cache: Surviving Operating System Crashes Chen Ng Rajamani and Aycock Mar, 96 11

CSE-TR-287-96 Impact of Selection Functions on Routing Algorithms Performance in Multicomputer Networks Feng and Shin Mar, 96 18

CSE-TR-288-96 Induction: Inference and Process Rothleder Mar, 96 12

CSE-TR-289-96 ISMAUT Tools: A Software Tool Kit for Rational Tradeoffs Among Conflicting Objectives D'Ambrosio Mar, 96 9

CSE-TR-290-96 Corona: A Communication Service for Scalable Reliable Group Collaboration Systems (Preliminary Design) Hall Mathur Jahanian Prakash and Ramussen Mar, 96 14

CSE-TR-291-96 RTCAST: Lightweight Multicast for Real-Time Process Groups Abdelzaher Shaikh Jahanian and Shin Apr, 96 26

CSE-TR-292-96 GRASP - - A New Search Algorithm for Satisfiability Silva and Sakallah Apr, 96 17
This report introduces GRASP (Generic seaRch Algorithm for the Satisfiability Problem), an integrated algorithmic frame-work for SAT that unifies several previously propose search-pruning techniques and facilitates identification of additional ones. GRASP is premised on the inevitability of conflicts during search and it s most distinguishing feature is the augmentation of basic backtracking search with a powerful conflict analysis procedure. Analyzing conflicts to determine their causes enables GRASP to backtrack non-chronologically to earlier levels in the search tree, potentially pruning large portions of the search space. In addition, by ≥recording≤ the causes of conflicts, GRASP can recognize and preempt the occurrence of similar conflicts later on in the search. Finally, straightforward bookkeeping of the causality chains leading up toe conflicts allows GRASP to identify assignments that are necessary for a solution to be found. Experimental results obtained from a large number of benchmarks, including many from the field of test pattern generation, indicate that application of the proposed conflict analysis techniques to SAT algorithms can be extremely effective for a large number of representative classes of SAT instances.

CSE-TR-293-96 Optiming Delay in Delayed-Write File Systems Chen May, 96 12

CSE-TR-294-96 Goal-Directed Performance Tuning for Scientific Applications Shih Jun, 96 135

CSE-TR-295-96 Modeling Domino Logic for Static Timing Analysis VanCampenhout Mudge and Sakallah Jun, 96 9

CSE-TR-296-96 Timing Analysis of Domino Logic VanCampenhout Mudge and Sakallah Jun, 96 8

CSE-TR-297-96 Performance of a Distributed Object-Based Internet Collaboratory Malan Jahanian Rasmussen and Knoop Jul, 96 21

CSE-TR-298-96 Experiments on Six Commercial TCP Implementations Using a Software Fault Injection Tool Dawson Jahanian and Mitton Jul, 96 20

CSE-TR-299-96 Optimal Zero-Aliasing Space Compaction of Test Response Chakrabarty Murray and Hayes Aug, 96 26

CSE-TR-300-96 A Cellular Wireless Local Area Network with QoS Guarantees for Heterogeneous Traffic Choi and Shin Aug, 96 24

CSE-TR-301-96 Using Stall Cycles to Improve Microprocessor Performance Dundas and Mudge Sep, 96 23

CSE-TR-302-96 The Satisfiability-Indicating Multi-Index Organization for Maintaining Materialized Path Query OODB Views Kuno and Rundensteiner Sep, 96 25

CSE-TR-303-96 Sectored Cache Performance Evaluation: A case study on the KSR-1 data subcache Rivers and Davidson Sep, 96 13

CSE-TR-304-96 Design Issues on the Support of Tools and Media in Replayable Workspaces Manohar and Prakash Sep, 96 15

CSE-TR-305-96 Preliminary Analytical Approach to a Brachiation Robot Controller Nakanishi Fukude and Koditschek Sep, 96 23

CSE-TR-306-96 Tagless Two-level Branch Prediction Schemes Chen Lee Postiff and Mudge Sep, 96 18

CSE-TR-307-96 An Agent Model for Distributed Part-Selection Darr and Birmingham Sep, 96 10

CSE-TR-308-96 Query Processing in the MultiMedia Visual Information Seeking Environment: A Comparative Evaluation Hibino and Rundensteiner Oct, 96 17

CSE-TR-309-96 Learning Procedural Planning Knowledge in Complex Environments Pearson Oct, 96 158

CSE-TR-310-96 Signal Delay in Coupled Distributed RC Lines in the Presence of Temporal Proximity Chandramouli Kayssi and Sakallah Oct, 96 19
With improvements in technology, accurate delay modeling of interconnects is becoming increasingly important. Due to decreasing feature sizes, the spacing between the signal lines is also decreasing. Consequently, the switching activities on the neighboring lines can have a significant impact on the delay of the line of interest, and can no longer be ignored. Accurate modeling of this phenomenon, which we call the proximity effect, is the subject of this paper. This is similar to the state-dependency of logic gate delays, where signal delay can be affected by the switching activities on the side inputs of a gate. We describe an efficient and accurate delay computation method using precomputed interconnect moments that treats the coupled lines as uniform, distributed RC lines and does not make any lumped approximations. This allows the proposed delay model to be used in a timing analysis tool operating over both gate and interconnect domains while accounting for state-dependency.

CSE-TR-311-96 The Dynamic Information Integration Model Nica and Rundensteiner Oct, 96 37

CSE-TR-312-96 TCP Enhancement for an Integrated Services Internet Feng Kandlur Saha and Shin Oct, 96 24

CSE-TR-313-96 Workshop on Databases: Active and Real-Time 1996 (Concepts meet Practice) Soparkar and Ramamritham Nov, 96 107

CSE-TR-314-96 Specification of the PUMA memory management design Jacob and Mudge Nov, 96 17

CSE-TR-315-96 Extended Aggregation Relationships for Process Specification and Enactment in Active Databases Chaudhry Moyne and Rundensteiner Nov, 96 18

CSE-TR-316-96 A Name-Based Mapping Scheme for Rendezvous Thaler and Ravishankar Nov, 96 26

CSE-TR-317-96 Early Design Cycle timing Simulation of Caches (Preliminary Exam Report) Tam and Davidson Nov, 96 71

CSE-TR-318-96 ORCHESTRA: A Fault Injection Environment for Distributed Systems Dawson Jahanian and Mitton Nov, 96 30

CSE-TR-319-96 An Instruction Stream Compression Technique (U of M Confidential) Bird and Mudge Nov, 96 21

CSE-TR-320-96 Broy-Lamport Specification Problem: A Gurevich Abstract State Machine Solution (Update to 223-94) Huggins Dec, 96 16

CSE-TR-321-96 Specification and Verification of Pipelining in the ARM2 RISC Microprocessor Huggins and VanCampenhout Dec, 96 35
Gurevich Abstract State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a pipelined microprocessor (an ARM2 implementation) is described. Both the sequential execution model and final pipelined model are formalized using ASMs. A series of intermediate models are introduced that gradually expose the complications of pipelining. The first intermediate model is proven equivalent to the sequential model in the absence of structural, control, and data hazards. In the following steps, these simplifying assumptions are lifted one by one, and the original proof is refined to establish the equivalence of each intermediate model with the sequential model, leading ultimately to a full proof of equivalence of the sequential and pipelined models.

CSE-TR-322-96 Recursive Abstract State Machines Gurevich and Spielmann Dec, 96 14

CSE-TR-323-96 On-Line Extraction of SCSI Disk Drive Parameters Worthington Ganger Patt and Wilkes Dec, 96 38

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