Abstract State Machines


Subjects

Methodology

Applications

ASM Studies

VHDL'93


Citation: Egon Börger, Uwe Glässer, and Wolfgang Muller, "Formal Definition of an Abstract VHDL'93 Simulator By EA-Machines", in C. Delgado Kloos and P.T. Breuer, eds., Formal Semantics for VHDL, Kluwer Academic Publishers, 1995, pp. 107-139.
Summary: A formal semantics for VHDL'93, including: signals, time, variables, and ports.
Subjects: VHDL
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