Breakfast, Registration

8:45 - 9:15 a.m. (Auditorium 2)

Welcoming Remarks

Pramod Khargonekar, Chair EECS Dept.

Naveed Sherwani, Chair Steering Committee

9:15 - 12:30 p.m. (Auditorium 2)

Kensall D. Wise

10:30 - 11:00 a.m.

Coffee Break

1.2 High Performance Options Through Nanoelectronics

Gernot Pomerenke

1.3 Retrospective on VLSI Adventures

Lynn Conway

12:30 - 2:00 p.m. (Salon II & III)

Lunch

2:00 - 4:00 p.m. (Auditorium 2)

2A.1 PASTA: Partial Scan to Enhance Test Compaction

Irith Pomeranz, Sudhakar M. Reddy

2A.2 On Applying Set Covering Models to Test Set Compaction

Paulo F. Flores, Horácio C. Neto, João P. Marques-Silva

2A.3 On Test Generation with a Limited Number of Tests

Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita

2A.4 Functional ATPG for Delay Faults

M. Michael, S. Tragoudas

2A.5 On Path Delay Fault Testing of Multiplexer-Based Shifters

H. T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, M. Nicolaidis

2A.6 A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation

P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch

2:00 - 4:00 p.m. (Conference F)

2B.1 VLSI Implementation of Early Branch Prediction Circuits for High Performance Computing

Aamir A. Farooqui, Voijin G. Oklobdzija

2B.2 The Design of a Register Renaming Unit

B. Bishop, T. Kelliher, M. J. Irwin

2B.3 Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit Applications

O. Hauck, M. Garg, S. A. Huss

2B.4 Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM

Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch

2B.5 Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation

Janardhan H. Satyanarayana, Keshab K. Parhi

2B.6 Adaptive Hard Disk Power Management on Personal Computers

Yung-Hsiang Lu, Giovanni De Micheli

4:00 - 4:30 p.m.

Coffee Break

4:30 - 5:50 p.m. (Auditorium 2)

3A.1 Inductance Effects in RLC Trees

Yehea I. Ismail, Eby G. Friedman, Jose L. Neves

3A.2 S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric

Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi

3A.3 ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment

Yanhong Yuan, Prithviraj Banerjee

3A.4 An Exact Analytical Time-Domain Model of Distributed Interconnects for High Speed Nonlinear Circuit Application

Ninglong Lu, Ibrahim N. Hajj

4:30 - 5:50 p.m. (Conference F)
 

3B.1 A Radix-16 SRT Division Unit with Speculation of the Quotient Digits

Gianluca Cornetta, Jordi Cortadella

3B.2 Area-Efficient Area Pad Design for High Pin-Count CMOS VLSI Chips

Louis Luh, John Choma Jr., Jeffrey Draper

3B.3 New 2 Gbits/s CMOS I/O Pads

G. Masera, G. Piccinini, M. Ruo Roch, M. Zamboni

3B.4 A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning

Jörg Henkel

7:00 - 9:00 p.m. (Salon IV)

Cocktail Party

Breakfast

8:30 - 10:30 a.m. (Auditorium 2)

4A.1 On Optimizing Test Strategies for Analog Cells

Anna M. Brosa, Joan Figueras

4A.2 Novel Design for Testability of a Mixed-Signal VLSI IC

E. McShane, K. Shenai, L. Alkalai, E. Kowala, V. Boyadzhyan, B. Blaes, W. C. Fang

4A.3 The Development of Analog SPICE Behavioral Model Based on IBIS Model

Ying Wang, Han Ngee Tan

4A.4 Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits

Mostafa Abd-El-Barr, Yanbing Xu, Carl McCrosky

4A.5 Fault Coverage Estimation for Early Stages of VLSI Design

Von-Kyoung Kim, Tom Chen, Mick Tegethoff

4A.6 Pseudo-Exhaustive Testing of Sequential Circuits

Bassam Shaer, Sami A. Al-Arian, David Landis

8:30 - 10:30 a.m. (Salon I)

4B.1 Molecular Electronics: A Review and Prospectus

James Ellenbogen

4B.2 Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic Circuits

D. B. Janes, V. P. Roychowdhury, S. Datta, J. M. Woodall, M. R. Melloch, E. L. Peckham, En-Hsing Chen, B. L. Walsh, M. Batistuta, R. P. Andres, Jia Liu, R. Reifenberger, Takhee Lee, C. P. Kubiak, B. T. Kasibhatla

4B.3 QCA Circuits

Mike Niemer, Peter Kogge

4B.4 Why is Time-Varying Control Necessary for Signal Processing with Locally Connected Quantum-Dot Arrays?

Arpád I. Csurgay, Craig S. Lent, Wolfgang Porod

4B.5 Transport in Split Gate MOS Quantum Dot Structures

S. M. Goodnick, J. Bird, D. K. Ferry, A. D. Gunther, M. D. Khoury, M. Kozicki, M. J. Rack, T. J. Thornton, D. Vasileska-Kafedezka

4B.6 Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the Multi-GHz Domain

T. P. E. Broekaert, B. Brar, F. Morris, A. C. Seabaugh, G. Frazier

10:30 - 11:00 a.m.

Coffee Break

11:00-12:40 p.m. (Auditorium 2)

5A.1 Efficient Algorithms for Finding Highly Acceptable Designs based on Module-Utility Selections

Chantana Chantrapornchai, Edwin H.-M. Sha, Xiabo (Sharon) Hu

5A.2 Reducing BDD Size by Exploiting Structural Connectivity

Ronnie L. Wright, Michael A. Shanblatt

5A.3 An Integrated Approach for Synthesizing LUT Networks

Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya

5A.4 Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops

Abhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri

5A.5 Design Issues in the Synthesis of Reusable Cores

Rohit Sharma, C. P. Ravikumar

11:00-12:40 p.m. (Salon I)

5B.1 Ultrahigh-Speed Circuits Using Resonant Tunneling Diodes

M. Yamamoto

5B.2 A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTs

H. Matsuzaki, T. Itoh, M. Yamamoto

5B.3 Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit

Tetsuya Uemura, Pinaki Mazumder

5B.4 Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High Speed Digital Circuit Applications

P. Fay, G. H. Bernstein, D. Chow, J. Schulman, P. Mazumder, W. Williamson, and B. Gilbert

5B.5 A Memory Design in QCAs Using the SQUARES Formalism

D. Berzon, T. J. Fountain

12:40 - 2:00 p.m. (Salon II & III)

Lunch

2:00-4:00 p.m. (Auditorium 2)

6A.1 Transistor Level Synthesis for Static CMOS Combinational Circuits

Chia-Pin R. Liu, Jacob A. Abraham

6A.2 SINMEF - A Decomposition Based Synthesis Tool for Large FSMs

Carlos Humberto Llanos Quintero, Marius Strum

6A.3 Test and Evaluation Approach on Safety-Critical Software

Weiwei Li, Zhongwei Xu, Haiying Tu, Yan Jin

6A.4 Design Recovery for Incomplete Combinational Logic

Travis Doom, Anthony Wojcik, Moon-Jung Chung

6A.5 Regression-Based Macromodeling for Delay Estimation of Behavioral Components

A. Macii, E. Macii, G. Odasso, M. Poncino, R. Scarsi

6A.6 Efficiently Searching the Optimal Design Space

Stephen Blythe, Robert Walker

2:00-4:00 p.m. (Salon I)

6B.1 A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH Technique

Yiu (Simon) Wu, John Ling, Ward J. Helms

6B.2 No-Race Charge-Recycling Differential Logic (NCDL)

Seung-Moon Yoo, Sung-Mo (Steve) Kang

6B.3 Linear Transconductors Using Low Voltage Low Power Square-Law CMOS Cells

Tuna B. Tarim, Mohammad Ismail

6B.4 Current Sensor on the Base of Permanent Prechargeable Amplifier

Victor Varshavsky, Masayuki Tsukisaka

6B.5 Parallel Saturating Fractional Arithmetic Units

Navindra Yadav, Michael Schulte, John Glossner

6B.6 Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation

Shugang Wei, Kensuke Shimizu

2:00 - 4:00 p.m. (Conference D)

6C.1 Model Evaluation Using Genetic Manipulation Techniques

Z. Stamenkovic, H.-Ch. Dahman, U. Glaeser

6C.2 A Genetic Algorithm for Register Allocation

K. M. Elleithy, E. G. AbdelFattah

6C.3 Congestion Mitigation During Placement

Kanad Chakraborty, Natesan Venkateswaren

6C.4 A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate Arrays

John Karro, James Cohoon

6C.5 Formal Verification of Tree-Structured Carry-Lookahead Adders

Sae Hwan Kim, Shiu-Kai Chin

6C.6 Bounding Algorithms for Design Space Exploration

Samit Chaudhuri, Robert Walker

6C.7 Digital Neural Processing Unit for Electronic Nose

Hoda S. Abdel-Aty-Zohdy, Mohmoud Al-Nsour

6C.8 A Low Power Charge-Recycling CMOS Clock Buffer

Xiaohui Wang, Wolfgang Porod

6C.9 A Multiple-Input Single-Phase Clock Flip-Flop Family

Richard F. Hobson, Allan R. Dyck

6C.10 Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs

I. Lemberski

6C.11 VHDL Design of a Test Processor based on Mixed-Mode Test Generation

Md. Altaf-Ul-Amin, Zahari Mohamed Darus

4:00 - 4:30 p.m.

Coffee Break

4:30 - 5:50 p.m. (Auditorium 2)

7A.1 An Incremental Floor Planner

James Crenshaw, Majid Sarrafzadeh, Pradeep Prabhakaran, Prithviraj Banerjee

7A.2 A Greedy Router with Technology Targetable Output

R. Balakrishnan, R. F. Hobson

7A.3 Routability Prediction for Hierarchical FPGAs

Wei Li, D. K. Banerji

7A.4 Memory Unit Design for Real Time DSP Applications

Daniel Chillet, Oliver Sentieys, Michael Corazza

4:30 - 5:50 p.m. (Salon I)

7B.1 Design Tools for MEMS/MST: Extending Mixed-Signal to Mixed-Technology

Bart Romanowicz, Stephen Bart, John Gilbert

7B.2 Design Automation of MEMS Systems Using Behavioral Modeling

Dennis Gibson, Alva Hare, Fred Beyette Jr., Carla Purdy

7B.3 Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics Systems

Robert L. Ewing

7B.4 Numerical Tools for Fracture of MEMs Devices

Noureddine Tayebi, Abdelkader Kamel Tayebi, Yacine Belkacemi

7:00 - 10:00 p.m. (Salon II & III)

Banquet

Breakfast

8:30 - 10:30 a.m. (Auditorium 2)

8A.1 Formal Checking of Properties in Complex Systems Using Abstractions

Dinos Moundanos, Jacob A. Abraham

8A.2 A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs

Subhashini Balakrishnan, Sofiène Tahar

8A.3 Symbolic Multi-Level Verification of Refinement

Stefan Hendricx, Luc Claesen

8A.4 Self-Checking of FGPA-Based Control Units

Ilya Levin, Vladimir Sinelnikov

8A.5 A Software Acceptance Test Technique based on Knowledge Accumulation

Yi Yu, Fangmei Wu

8A.6 A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability

Yong Chang Kim, Vishwani Agrawal, Kewel K. Saluja

8:30 - 10:30 a.m.  (Salon I)

8B.1 A Novel Low Power Low Phase-Noise PLL Architecture for Wireless Transceivers

Amr N. Hafez, Mohammed I. Elmasry

8B.2 NMOS Energy Recovery Logic

Chulwoo Kim, Seung-Moon Yoo, Sung-Mo (Steve) Kang

8B.3 Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems

Radu S. Secareanu, Ivan S. Kourtev, Eby G. Friedman, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier

8B.4 An All Digital BiCMOS Phase Lock Loop for VLSI Processors

Lim Chu Aun, S. M. Rezaul Hasan

8B.5 Low Power Techniques for Digital GaAs VLSI

J. F López, R. Sarmiento, A. Núñez

8B.6 A VLSI Architecture for ATM Algorithm-Agile Encryption

A. G. Wassal, M. A. Hasan

8:30 - 10:30 a.m. (Conference C)

8C.1 On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent's Rule

Dirk Stroobandt

8C.2 Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOS

E. McShane, K. Shenai, L. Alkalai, E. Kowala, V. Boyadzhyan, B. Blaes, W. C. Fang

8C.3 Low Power Design of an Acoustic Echo Canceller Gmdfa Algorithm on Dedicated VLSI Architectures

S. Gailhard, N. Julien, A. Baganne, E. Martin

8C.4 A Fully-Pipelined, 700 MByte/s DES Encryption Core

Ihn Kim, Craig S. Steele, Jeffrey G. Koller

8C.5 Proposal of Data-Driven Processor Architecture Qv-K1

Teruhiko Kamigata, Makoto Iwata, Koso Murakami, Hiroaki Terada

8C.6 Accurate Resource Estimation Algorithms for Behavioral Synthesis

Srinivas Katkoori, Ranga Vemuri

8C.7 Assessing Defect Coverage of Memory Test Algorithms

Von-Kyoung Kim, Tom Chen

8C.8 Memory Chip BIST: Architecture

Jacob Savir

8C.9 Exploiting Test Resource Optimization in Data Path Synthesis for BIST

Xiaowei Li, Paul Y. S. Cheung

8C.10 Resonant Tunneling Transistors for Threshold Logic Circuit Applications

Christian Pacha, Uwe Auer, Peter Glösekötter, Andreas Brenneman, Werner Prost, Franz-J. Tegude, Karl Goser

8C.11 A Multilevel Cache Memory Architecture for Nanoelectronics

D. Crawley

10:30 - 11:00 a.m.

Coffee Break

11:00 - 12:20 p.m. (Auditorium 2)

9A.1 ALPS: A Peak Power Estimation Tool for Sequential Circuits

F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante

9A.2 Clustered Table-Based Macromodels for RTL Power Estimation

Roberto Corgnati, Enrico Macii, Massimo Poncino

9A.3 The Design of a CMOS Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement Circuits

Yuyu Chang, John Choma Jr., Jack Wills

9A.4 A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem

Yuke Wang, Xiaoyu Song, Mostapha Aboulhamid

11:00 - 12:20 p.m. (Salon I)

9B.1 Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method

Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada

9B.2 A 1.8 V High Dynamic-Range CMOS High-Speed Four Quadrant Multiplier

Chi-Hung Lin, Mohammad Ismail

9B.3 A Second-Order Sigma-Delta Modulator with Built-in VGA to Improve SNR and Harmonic Distortion

Xiaopeng Li, Mohammad Ismail

9B.4 A Novel Low Power Energy Recovery Full Adder Cell

R. Shalem, E. John, L. K . John

12:25 - 12:35 p.m. (Auditorium 2)

Closing Remarks

Pinaki Mazumder, Program Chair

12:45 - 2:00 p.m. (Salon II & III)

Lunch