Thursday, February 25
4:30 - 5:30 PM
Room 1001 EECS
Abstract-
This talk first describes the circuit design and the
preliminary
experimental results of a family of precision comparators
which allows
level crossing times to characterize a communications signal
(e.g., a high
frequency, narrow bandwidth IF). A comparator divides the
continuous range
of an analog input signal into two regions and provides a
digital output
indicating the region in which the signal is. This digital
output must,
by definition, have an extremely short transition time. A
comparator is
thus a slope amplifier, since a slowly varying input must
produce a very
rapidly varying output. Noise in the amplifiers causes the
output
transition to be jarred from its correct position, producing
jitter in the
output.
The talk presents a circuit design for very low jitter
comparators. One
of these comparators has been assembled; its performance is
vastly superior
to conventional instrumentation. The immediate application
of these devices
is to miniature, low power communications and navigation
receivers; the
results, however, are easily adapted to general purpose wave
form
digitization. Comparators requiring low jitter are, of
course, key
components of more conventional analog to digital conversion
systems, e.g.,
flash analog to digital converters are composed of an array
of comparators
with different thresholds.
These comparators will be used in communications receivers
processing short
messages, and the second, very different, part of the talk
presents tight
upper and lower bounds on the performance of coding when the
number of
information bits in a code word is small.