TAU 97 Advance Program
Advance Program
Thursday, December 4
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7:30-8:30am: Breakfast/Registration
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8:30-10am: Session 1 -- Static Timing Analysis
Chair: David Hathaway, IBM
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(Invited) Worst-Case Static Timing Analysis--From Gates to
Instructions
Sharad Malik, Princeton U.
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AFTA: A Delay Model for Functional Timing Analysis
V. Chandramouli, Jesse Whittemore, Karem Sakallah, U. Michigan
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Statistical Delay Calculation, a Linear Time Method
Michel Berkelaar, Eindhoven U. of Tech.
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10-10:30am: Coffee Break
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10:30am-12pm: Session 2 -- Synthesis and Timing
Chair: Tom Shiple, Synopsys
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(Invited) Impact of Small Geometries on Timing-Driven Synthesis
Kurt Keutzer, Synopsys
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Efficient Modeling of Memory Arrays with Timing Requirements in
Symbolic Ternary Simulation
Miroslav Velev, Randal Bryant, Carnegie Mellon U.
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An Overview of Prediction-Based Architectural Retiming
Soha Hassoun, Tufts U.; Carl Ebeling, U. Washington
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12-1pm: Lunch
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1-2pm: Session 3 -- Posters
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Timing-Driven High-Level Synthesis Using Tabu Search Heuristics
Jonas Hallberg, Zebo Peng, Linköping U.
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Satisfiability Models and Algorithms for Circuit Delay Computation
Luis Guerra e Silva, João Marques Silva, Luis Miguel Silveira,
Cadence European Laboratories/INESC; Karem Sakallah,
U. Michigan
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Clock-Routing Driven Layout Methodology for Semi-Synchronous
Circuit Design
Atsushi Takahashi, Wataru Takahashi, Yoji Kajitani, Tokyo Inst. of Tech.
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Static Timing Verification of Asynchronous Circuits
Joram Peer, Iaacov Kobrinsky, National Semiconductor
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RCL: Generating a Reduced Cell Library for Early Timing Estimation
and Library Exploration Using Logic Synthesis
John Croix, Advanced Micro Devices
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Approximate Time Separation of Events in Practice
Supratik Chakraborty, Stanford U.;
Pasupathi Subrahmanyam, Bell Labs, Lucent Technologies;
David Dill, Stanford U.
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A Practical Approach to Wire-Sizing for Path Delay and Skew
Reduction in Clock Trees
Bob Waldron, Cari Pederson, Symbios Logic
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Timing Issues in Static-Dynamic Synthesis
Ruchir Puri, Kenneth Shepard, IBM
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Delay and Power Calculation Using DPC and DCL
Jay Abraham, Don Cottrell, SI2
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On Path Delay Untestability and Stuck-Fault Redundancy
S. Majumder, Rutgers U.;
V. Agrawal, Bell Labs, Lucent Technologies;
M. Bushnell, Rutgers U.
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2-3:30pm: Session 4 -- High-Speed Timing Issues
Chair: Larry Pileggi, Carnegie Mellon U.
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(Invited) Timing Analysis of High-Speed VLSI Designs--Trends and
Challenges
Stefan Rusu, Intel
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3-sigma Worst-Case Calculation of Delay and Crosstalk for Critical
Net
Norman Chang, Valery Kanevsky, Bill Queen, O. Sam Nakagawa, Soo-Young Oh, Hewlett-Packard
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Incorporating Signal Dependencies into Transistor-Level Delay
Calculation
Timothy Burks, Robert Mains, IBM
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3:30-4pm: Coffee Break
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3:30-4:30pm: Session 5 -- Posters
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Retiming DAGs
P. Calland, A. Mignotte, O. Peyran, Y. Robert, F. Vivien, École Normale Supérieure de Lyon
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Salphasic Clock Planes - A Novel Clocking Method
Vernon Chi, U. North Carolina, Chapel Hill
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Retiming Level-Clocked Circuits for Latch Count Minimization
Naresh Maheshwari, Iowa State U.;
Sachin Sapatnekar, U. Minnesota
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System Synthesis Based on Reusable High Level Building Blocks
Jens Horstmannshoff, Thorsten Grötker, Heinrich Meyr, Aachen U. of Tech.
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Implementation and Comparative Analysis of an Efficient Polynomial
Response Generator Structure
Ali Mirmassoumi, Olli Vainio, Tapio Saramäki, Tampere U. of Tech.
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An Integrated Approach for Net Parasitic Extraction
V. Chandramouli, Lucent Technologies; Nagaraj NS,
SEMATECH; Ram Swaminathan, Chi-Yuan Lo, Lucent Technologies
; Jesse Lu, OEA International; Weikai Sun, Ultima
Interconnect Technologies; Don Cottrell, Silicon Integration
Initiative
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Removing False Paths from Combinational Modules
Yuji Kukimoto, Robert Brayton, U. California, Berkeley
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Topological Synthesis of Clock Trees with Non-Zero Clock Skew
Ivan Kourtev, Eby Friedman, U. Rochester
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Experiments in the Iterative Application of Resynthesis and
Retiming
Soha Hassoun, Tufts U.; Carl Ebeling, U. Washington
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Wire Delay in the Presence of Crosstalk
Gin Yee, U. Washington;
Rajit Chandra, Vidyasagar Ganesan, Sun Microsystems;
Carl Sechen, U. Washington
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6:30-9pm: Banquet at the Hyatt Regency Austin
Friday, December 5
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7:30-8:30am: Breakfast
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8:30-10am: Session 6 -- Asynchronous Timing
Chair: Steven Nowick, Columbia U.
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Response Time Properties of Linear Pipelines with Varying Cell
Delays
Robert Berks, Jo Ebergen, U. Waterloo
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A Technique for Finding and Verifying Speed-Dependences in Gate
Circuits
Radu Negulescu, U. Waterloo
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Timed Event/Level Structures
Wendy Belluomini, Chris Myers, U. Utah
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Practical Timing Analysis of Asynchronous Systems Using Time
Separation of Events
Supratik Chakraborty, Stanford U.;
Kenneth Yun, U. California, San Diego;
David Dill, Stanford U.
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10-10:30am: Coffee Break
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10:30am-12pm: Session 7 -- Timing and Formal Verification
Chair: Alexander Ishii, NEC
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(Invited) Formal Verification of Timed Circuits
Rajeev Alur, U. Pennsylvania
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Making Complex Timing Relationships Readable: Presburger Formula
Simplification Using Don't Cares
Tod Amon, Southwest Texas State U.; Gaetano Borriello,
U. Washington; Jiwen Liu, Southwest Texas State U.
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Computing Delay with Coupling Using Timed Automata
Serdar Tasiran, Robert Brayton, U. California, Berkeley
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12-1pm: Lunch
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1-2:30pm: Session 8 -- Timing Issues in Synthesis/Placement
Chair: Sharad Malik, Princeton U.
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(Invited) Next Generation Logic Synthesis for DSM
Robert Brayton, U. California, Berkeley
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A Stochastic Approach to Timing-Driven Partitioning and Placement
with Accurate Net and Gain Modeling
Shantanu Dutt, U. Illinois, Chicago
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Table-Lookup Methods for Improved Performance-Driven Routing
John Lillis, U. Illinois, Chicago;
Premal Buch, U. California, Berkeley
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2:30-3pm: Coffee Break
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3-4:30pm: Session 9 -- Coupling as it Impacts Timing
Chair: Timothy Burks, IBM
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(Invited) Technology Trends for Timing Analysis in Deep Submicron
Digital Integrated Circuits
Kenneth Shepard, IBM
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Noise Expressions for Capacitance Coupled Distributed RC Lines
Hiroshi Kawaguchi, Takayasu Sakurai, U. Tokyo
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Network Reduction for Crosstalk Analysis in Deep Submicron
Technologies
Davide Pandini, Primo Scandolara, Carlo Guardiani, SGS Thomson
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4:30pm: Adjourn