Part: PUMA_FXU
Deposit Date: 01.28.04
Process Technology: TSMC 0.18
Type: Soft
Design: Verilog - Standard Cell
Designer: Jayakumaran Sivagnaname and Rahul Rao
Affiliation: University of Michigan
Qualification: Pre-Silicon Verified
Instantiated: Yes
Patent: None
Description: A dual-issue 4-way superscalar PowerPC fixed-point unit processor that implements majority of instructions in the PowerPC ISA.

Part: WIMS
Deposit Date: 02.05.04
Process Technology: TSMC 0.18
Type: Soft
Design: Verilog - Standard Cell
Designer: Eric Marsman and Robert Senger
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: The WIMS microcontroller is a 16-bit 3-stage pipeline with a 24-bit address space. This is a custom ISA. The chip also instantiates some analog components, 64KB of on-chip memory, and a 512 byte loop cache.