Part: APR
Deposit Date: 01.05.04
Process Technology: TSMC 0.18
Type: Design Methodology
Designer: Eric D. Marsman and Robert M. Senger
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: A design flow built for TSMC 0.18um using Cadence Silicon Ensemble. It has options/directions for both Standard Top Metal (STM) and Thick Top Metal (TTM) process options. The following UMIPS entries are referenced in this flow and should also be checked out: FIX_VER_CLK_TREE, LEF_SCRIPTS, CALIBRE_DRC_LVS, TSMC18_LIB, METAL_FILL.

Part: TSMC18_LIB
Deposit Date: 01.05.04
Process Technology: TSMC 0.18
Type: Design Methodology
Designer: Eric D. Marsman
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: Some of the TSMC18 files for use in APR, DRC, LVS, including updated padframe. Some modifcations for the thick top metal (TTM) option are included and syntax changes for use with tools.