Part: MULT_GEN
Deposit Date: 06.27.03
Type: Design Tools
Designer: James E. Stine and Olivier M. Duverne
Affiliation: Illinois Institute of Technology
Qualification: Pre-Silicon Verified
Instantiated: No
Patent: None
Description: Perl scripts for generation of parallel multiplier verilog RTL modules. Can generate Dadda and Array multipliers with or without truncation. A C program is also provided for analysis of truncation error.

Part: FIX_VER_CLK_TREE
Deposit Date: 01.05.04
Type: Design Scripts
Designer: Eric D. Marsman
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: A script to change the net and cell names, not the structure, of the clk tree in the verilog file to match the dspf file. For some reason, sedsm outputs them differently.

Part: LEF_SCRIPTS
Deposit Date: 01.05.04
Type: Design Scripts
Designer: Eric D. Marsman
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: Scripts for manipulation of LEF files for sedsm. For use with APR flow. Creates antenna lefs and modifies lower level modules power rings.