Part: MEMSINDUCTOR
Deposit Date: 08.04.03
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Michael S. McCorquodale
Affiliation: University of Michigan
Qualification: Pre-Silicon Verified
Instantiated: Yes
Patent: None
Description: A high Q MEMS 7.5nH suspended spiral inductor for clock synthesis, filters, etc.

Part: MEMSVARACTOR
Deposit Date: 07.30.03
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Michael S. McCorquodale
Affiliation: University of Michigan
Qualification: Pre-Silicon Verified
Instantiated: Yes
Patent: None
Description: A high Q MEMS 2pF suspended varactor for clock synthesis, filters, etc.

Part: 50OHM_OUTPUTDRIVER
Deposit Date: 07.25.03
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Michael S. McCorquodale
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: 50-ohm output driver used to drive up to 2pF at 1GHz.

Part: 50GSG100
Deposit Date: 04.18.03
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Michael S. McCorquodale
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: 50x50 micron ground-signal-ground (GSG) bonding pad with 100 micron pitch. This macro has been developed per Cascade Microtech's ACP GSG100 RF probe bondpad specification. The pad is passive and contains no ESD or other active devices.

Part: PAD50
Deposit Date: 04.18.03
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Michael S. McCorquodale
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: 50x50 micron bonding pad. The pad is passive and contains no ESD or other active devices.

Part: TSMC18_LIB
Deposit Date: 01.05.04
Process Technology: TSMC 0.18
Type: Design Methodology
Designer: Eric D. Marsman
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: Some of the TSMC18 files for use in APR, DRC, LVS, including updated padframe. Some modifcations for the thick top metal (TTM) option are included and syntax changes for use with tools.

Part: METAL_FILL
Deposit Date: 01.05.04
Process Technology: TSMC 0.18
Type: Hard
Design: Full-Custom
Designer: Eric D. Marsman
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: A large and small metal fill cell for increasing metal density for CMP DRC rules . These cells short the node to the substrate and are built to be put into arrays. Designed for TSMC18 process with Thick Top Metal (TTM) option.

Part: PUMA_FXU
Deposit Date: 01.28.04
Process Technology: TSMC 0.18
Type: Soft
Design: Verilog - Standard Cell
Designer: Jayakumaran Sivagnaname and Rahul Rao
Affiliation: University of Michigan
Qualification: Pre-Silicon Verified
Instantiated: Yes
Patent: None
Description: A dual-issue 4-way superscalar PowerPC fixed-point unit processor that implements majority of instructions in the PowerPC ISA.

Part: WIMS
Deposit Date: 02.05.04
Process Technology: TSMC 0.18
Type: Soft
Design: Verilog - Standard Cell
Designer: Eric Marsman and Robert Senger
Affiliation: University of Michigan
Qualification: Post-Silicon Verified
Instantiated: Yes
Patent: None
Description: The WIMS microcontroller is a 16-bit 3-stage pipeline with a 24-bit address space. This is a custom ISA. The chip also instantiates some analog components, 64KB of on-chip memory, and a 512 byte loop cache.