Contributing IP to UMIPS is a prestigious undertaking. Your contribution makes research at the University of Michigan better for yourself and for others. However, contributing is a significant undertaking and it cannot be taken lightly. If you expect researchers to use your IP, it must be delivered correctly. In a nutshell, do it right the first time.

All submitted IP will undergo an audit by the development team. During this audit, the deliverables will be thoroughly evaluated. Only submitted IP that passes the audit will be included in the repository. Contributors may resubmit rejected IP, but no more than ONE resubmission is permitted per design. Audits are anticipated to occur every Friday, time permitting. If an IP block is rejected, the terms under which it will be accepted will be reported clearly to the submitting party. In order to pass the audit successfully the first time, please refer to the Deliverables section that follows prior to submission.

UMIPS is in the process of managing awards for the most highly utilized IP macros and for the highest quality submissions.

UMIPS will manage design methodology IP for ECAD. This includes documents describing IC design flows, scripts commonly utilized in design flows, or tools used to generate design(s). Deliverables include:

• README
  A text file describing each and every file that will be included in the repository. The README must include the desginer name, affiliation, and contact information. Contact information will NOT be available on the website. Click here for a sample.

• Detailed Proprietary Description
  A text file containing a detailed description of the methodology or script(s) and its application. This description will NOT be available on the website.

• Short Nonproprietary Description
  A text file containing a description of the methodology or script(s) and its application. This will be the description available on the website. Click here for samples.

The following deliverables must be included with ALL soft and hard IP submissions.

• README
  A text file describing each and every file that will be included in the repository. The README must include the desginer name, affiliation, and contact information. Contact information will NOT be available on the website. Click here for a sample.

• Detailed Proprietary Description
  A text file containing a full and detailed description of the macro that includes specific details of the implementation. A detailed specification of the part from either simulation or test should be included. Timing diagrams and a complete specification of the interface, including a description of all pins and any standard protocols used, is mandatory. This description will NOT be available on the website.

• Short Nonproprietary Description
  A text file containing a description of the macro that does not divulge any specific details of the implementation. This will be the description available on the website. Click here for samples.

Additional Deliverables for Soft IP

The following deliverables, in addition to the baseline deliverables, are required for soft IP submissions.

• Synthesizable HDL
  Synthesizable code describing the macro in HDL

• Test Fixture and Vectors
  An HDL test fixture including stimulus vectors for user test of the macro

• Synthesis Scripts
  Synthesis scripts that define clocks, pin timing, load constraints, false paths, synthesis commands, and any other special requirements. Static timing analysis scripts and constraints are also required.

• Process Specific Details
  Include information on hard instantiated cells, dont_use cells, memory or other marcro blocks used, and suggested wire load models. If applicable, include APR scripts.

Additional Deliverables for Hard IP

The following deliverables, in addition to the baseline deliverables, are required for hard IP submissions although in some instances, not every item here is pertinent to the submitted design. Use sound  judgment when making decisions regarding this. For example, a passive bondpad will not require a netlist or LVS verification. It will require every other item listed below.  

• Netlist
  A hierarchical netlist for the macro in SPICE format

• Physical Design
  A GDS or CIF file for the physical design of the macro

• Map Table
  The map table for GDS or CIF stream generation specific to the process technology

• Routing File
  A LEF file for automatic place and route (APR) of the macro

• Verification Reports
  LVS and DRC reports are mandatory. ERC, metal fill, and others are optional. Known errors must be clearly explained in the README file.

• Verification Decks
  The exact decks used for verification must be included. Edits to the baseline deck for the process technology must be clearly explained in the README file.

Pre-Silicon IP is simply IP that has been simulated for functionality and performance, but not yet verified by test of fabricated silicon. There are no requirements beyond the deliverables listed above for Pre-Silicon IP.

Post-Silicon Verified IP

Post-Silicon Verified IP has been fabricated and tested. To achieve Post-Silicon Verified status is nontrivial as it clearly indicates the validity of the IP. The details of Post-Silicon verification will be available shortly.

Instantiated IP

IP components are also qualified as either "instantiated" or "uninstantiated" components. This metric determines if the component has been developed into a larger design. Instantiated components have been through at least one design cycle and thus the deliverables have been utilized for development, which indicates the repository deliverables are adequate for design.

Submission

Submit your deliverables to umips-devteam@umich.edu. You will be contacted within one week with an audit date.