From Analog to Digital

In the decade or so significant research efforts have been focused on exploring digitally- intensive or all-digital implementations for traditionally analog systems. There are a number of factors, as below, driving this trend.

•  Traditionally all-analog systems do not take advantage of process scaling. In fact, analog design gets more challenging with scaling due to headroom, leakage and process limitations.

• Analog systems are always custom designed and cannot be ported between technology nodes without significant redesign.

• Custom layout in advanced processes gets progressively challenging as the number and compexity of design rule checks significantly increases. An automated (digital-like) design flows can simplify analog design procedure.

• Often it is difficult to integrate all-analog systems with digital systems because passive devices such as Inductors require a certain clearance.

All-digital implementations for traditionally analog systems often suffer from performance degradation due to various limitations of digital design. For example, in ADPLLs, quantization of phase detection (TDCs) and the digitally controlled oscillators (DCOs) directly impacts the inband noise.

Why VLSA?

We have adopted a new design methodology in an attempt to bridge the gap between traditionally analog and their new all-digital or digitally intensive counterparts. This methodology, namely very large scale analog (VLSA), seeks to improve the performance of all-digital implementations through exploration of new system architectures combined with very minimal(1 to 3 unit cells) custom design. Moreover, digital design flows such as synthesis and automatic place-and-route and utilized in order to simplify the design process.  This ensures that designs are portable as well as take advantage of improvements that process scaling brings.

The Methodology

• Come up with an all-digital or digitally-intensive architecture for traditionally all-analog systems. For example, an all-digital phase-locked loop.
• Identify the cells that can take advantage of careful custom design. For example, in an ADPLL, it is desireable to have careful design of the oscillator and the phase detection systems.
• Design and lay out the custom cells for the desired performance.
• Integrate the custom cells with digital design flows such as synthesis, APR, behavioral simulations.
• Write HDL code for the entire system.
• Perform sysnthesis and APR of the entire system followed by verification.