Description:

Verilog code for synthesizable ADPLL. 

Youngmin Park, 2010

 

Cell Library Used:

ARM Library Version X.X, TSMC 65nm CMOS

ARM RF Compiler Version X.X

 

Custom Cells Used:

BUFIZX8MA10TR (custom designed tri-state inverter cell)

 



Top Level Module:

core1 (core1.v)

 

Description of Files:



core1.v - TOP level ADPLL including register file

pll_core.v - Top level ADPLL w/o register file

rf_32.v - Register file (by ARM compiler, *not attached)

scan_cells.v - Scan chain unit cells

scan_chain_pll.v - Scan chain for ADPLL

subtract.v - Offset control block 

scaler.v - TDC coarse/fine code scaling block

modulator.v - DCO control modulator 

dlf.v - Loop filter

tdc.v - TDC 

ctrl_dco.v - DCO controller

counter.v - Counter for ring oscillator calibration

counter_div.v - Counter for divider

divider.v - Freq. divider

ring_osc.v - Ring oscillato