Description:

Verilog code for synthesizable TDC. 

Youngmin Park, 2010

 

Cell Library Used:

ARM Library Version X.X, TSMC 65nm CMOS

 

Custom Cells Used:

BUFIZX8MA10TR (custom designed tri-state inverter cell)

 



Top Level Module:

tdc (tdc.v)

 

Description of Files:

tdc.v - Top level TDC including scan chain

scan_cells.v - Scan chain unit cells

scan_chain_tdc.v - Scan chain for TDC

ring_osc_tdc.v - Ring oscillator

detect.v - Phase detection block

counter_tdc.v - Counter for calibratio