Description:

Verilog code for synthesizable UWB transmitter. 

Youngmin Park, 2009

 

Cell Library Used:

ARM Library Version X.X, TSMC 65nm CMOS

 

Custom Cells Used:

BUFIZX8MA10TR (custom designed tri-state inverter cell)



 

Top Level Module:

transmitter_core (transmitter_core.v)

 

Description of Files:

transmitter_core.v - Top level UWB transmitter (including scan chain)

transmitter.v - Top level UWB transmitter functional block 

counter.v - Counter for UWB transmitter calibration

custom.v - Behavioral model for custom tri-state inverter 

divider.v - Frequency divider

lfsr16.v - 16bit LSFR for data pattern generation

ppm.v - PPM modulator

ring_osc.v - Ring oscillator for center freq. control

scan_cells.v - Scan chain unit cell

scan_chain_ro_transmitter.v - scan chain for UWB transmitter

ring_osc_v2.v - Ring oscillator for BW contro