I am currently a graduate student in Computer Science Engineering at the University of Michigan. My research area is hardware verification, under Professor Valeria Bertacco in the Advanced Computer Architecture Laboratory (ACAL)

Eta Kappa Nu (HKN) engineering honor society is a group in which I am actively involved. After electing in in January 2005, I proudly served as Social Chair for a year.

My past research includes work at the Engineering Research Center for Reconfigurable Manufacturing systems ( ERC RMS) at the University of Michigan. This was an undergraduate project where I worked to verify an experimental laser measurement system which made use of several Position Sensitive Detector Arrays (PSD Array). PSDs are two-dimensional photodiodes which allow for the electronic detection of a laser's position on the semiconductor. Please refer to the paper for more information about this project.
Position Sensitive Detector (PSD) Paper

I designed and implemented a 64 bit out-of-order processor in Verilog HDL along with a group of four. This was my senior design project for my undergraduate degree in Electric Engineering. The processor implemented a subset of the Alpha ISA and included features such as

• An experimental on-chip hardware checker (see research section)
• This was a simple, efficient runtime verification unit that would verify certain parts of the instruction had executed properly and recover the core when an error was encountered
• Instruction and data caches
• Multiple execution units
• Early branch resolution
• Load Store Queue

For a digital circuits class, I designed a 4-bit array multiplier at the transistor level. The circuit was optimized for speed, power and glitch-free operation. Simulation was carried out with MATLAB and PSPICE.