OBJECTIVE

EDUCATION

PUBLICATIONS

Mike Schlansker, Dick Carter, Jayaram Mudigonda, Nathan Binkert, and Norm Jouppi. "The JNIC High-Performance Communication Software Architecture." Hewlett-Packard Tech Con, April 2007.

Nathan L. Binkert, Ali G. Saidi, and Steven K. Reinhardt. Integrated Network Interfaces for High-Bandwidth TCP/IP. The Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.

Taeho Kgil, Shaun D'Souza, Nathan Binkert, Ali Saidi, Ronald Dreslinski, Steve Reinhardt and Trevor Mudge PicoServer: The Benefits of 3D Stacking Technology for Low-Power High-Throughput Tier 1 Servers The Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2006.

Nathan L. Binkert, Ronald G. Dreslinski, Lisa R. Hsu, Kevin T. Lim, Ali G. Saidi, and Steven K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro Special issue on Architecture Simulation and Modeling, July/August 2006.

Nathan Lorenzo Binkert. Integrated System Architectures for High-Performance Internet Servers. Ph.D. Thesis. Department of Electrical Engineering & Computer Science, The University of Michigan. February 2006.

David W. Oehmke, Nathan L. Binkert, Steven K. Reinhardt, and Trevor Mudge. "How to Fake 1000 Registers." Proceedings of 38th Ann. International Symposium on Microarchitecture (MICRO), November 2005.

Ali G. Saidi, Nathan L. Binkert, Lisa R. Hsu, and Steven K. Reinhardt. "Performance Validation of Network-Intensive Workloads on a Full-System Simulator." Proceedings of the First Annual Workshop on Interaction between Operating System and Computer Architecture (IOSCA), pp. 33–38, October 2005.

Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt. "Performance Analysis of System Overheads in TCP/IP Workloads." Proceedings of 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), Sept. 2005.

Lisa R. Hsu, Ali G. Saidi, Nathan L. Binkert, and Steven K. Reinhardt. "Sampling and Stability in TCP/IP Workloads." Proceedings of the First Annual Workshop on Modeling, Benchmarking, and Simulation (MoBS), pp. 68–77, June 2005.

Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt. "Analyzing NIC Overheads in Network-Intensive Workloads." Proceedings of the Eighth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), February 2005.

Nathan L. Binkert, Ronald G. Dreslinski, Erik G. Hallnor, Lisa R. Hsu, Steven E. Raasch, Andrew L. Schultz, and Steven K. Reinhardt. "The Performance Potential of an Integrated Network Interface." Proceedings of the Advanced Networking and Communications Hardware Workshop (ANCHOR), June 2004.

Nathan L. Binkert, Erik G. Hallnor, and Steven K. Reinhardt. "Network-Oriented Full-System Simulation using M5." Proceedings of the Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW), pp. 36–43, February 2003.

Steven E. Raasch, Nathan L. Binkert, and Steven K. Reinhardt. "A Scalable Instruction Queue Design Using Dependence Chains." Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), pp. 318–329, May 2002.

Joel Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan Binkert, Roger Espasa, and Toni Juan. "ASIM: A performance model framework." IEEE Computer, February 2002.

Richard Weiss and Nathan Binkert. "A Comparison of AES Candidates on the Alpha 21264." Proceedings of the Third AES Candidate Conference, pp. 75–81, April 2000

TECHNICAL REPORTS

"A Simple Integrated Network Interface for High-Bandwidth Servers." Nathan L. Binkert, Ali G. Saidi, and Steven K. Reinhardt. University of Michigan Technical Report CSE-TR-514-06, January 2006.

Ali G. Saidi, Nathan L. Binkert, Lisa R. Hsu, and Steven K. Reinhardt. "Performance Validation of Network-Intensive Workloads on a Full-System Simulator." University of Michigan Technical Report CSE-TR-511-05, July 2005.

Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Ronald G. Dreslinski, Andrew L. Schultz, and Steven K. Reinhardt. "Analyzing NIC Overheads in Network-Intensive Workloads." University of Michigan Technical Report CSE-TR-505-04, December 2004.

David W. Oehmke, Nathan L. Binkert, Steven K. Reinhardt, and Trevor Mudge. "Design and Applications of a Virtual Context Architecture." University of Michigan Technical Report CSE-TR-497-04, September 2004.

TALKS

"Integrated Network Interfaces for High-Bandwidth TCP/IP." Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). San Jose, California. October 2006.

"Integrated Network Interfaces for High-Bandwidth TCP/IP." Invited talk at Intel Research China. Beijing, CHINA. September 2006.

"How to Fake 1000 Registers." Invited talk at Intel Research China. Beijing, CHINA. September 2006.

"Integrated System Architectures for High-Performance Internet Servers." Interview talk at Hewlett-Packard Labs. Palo Alto, California. June, 2006.

"Integrated System Architectures for High-Performance Internet Servers." Invited talk at Intel. Hillsboro, Oregon. February, 2006.

"How to Fake 1000 Registers." Paper presentation at the 38th Annual International Symposium on Microarchitecture (MICRO). Barcelona, SPAIN. November 14, 2005. (Awarded Best Presentation)

"Using the M5 Simulator." Invited talk at the First Workshop on Interaction between Operating System and Computer Architecture. Austin, Texas. October 8, 2005.

"Performance Analysis of System Overheads in TCP/IP Workloads." Paper presentation at the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT). St. Louis, Missouri. September 20, 2005.

"Redesigning Systems for High-speed Networking." Invited talk at Advanced Micro Devices. Sunnyvale, California. May 20, 2005.

"Using the M5 Simulator." Tutorial in conjunction with the 33rd Annual International Symposium on Computer Architecture (ISCA). Madison, Wisconsin. June 8, 2005.

"Analyzing NIC Overheads in Network-Intensive Workloads." Paper presentation at the Eighth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW). San Francisco, California. February 12, 2005.

"The Performance Potential of an Integrated Network Interface." Paper presentation at the Advanced Networking and Communications Hardware Workshop (ANCHOR). Munich, GERMANY. June 19, 2004.

"Towards Integrated System Architectures for High-Speed Networking." Invited talk at IBM. Yorktown Heights, New York. January 22, 2004.

"Network-Oriented Full-System Simulation using M5." Sixth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW). Anaheim, California. February 9, 2003.

"Operating System Changes for SMT Processors." Invited Presentation at Intel. Hillsboro, Oregon. October 11, 2002.

WORK EXPERIENCE

Hewlett-Packard Labs, Senior Research Scientist Sep. 2006–Present
Manager: Dr. Norm Jouppi—Director of the Advanced Architecture Lab, HP Fellow

• Nanophotonic Architectures: looking at future system architectures using on-chip and off-chip photonic interconnect.
• Coherent Attached NICs: designing systems with closely attached Ethernet controllers for high performance in-datacenter communications.
• Operating System support for Asymmetric Chip Multiprocessors.

Arbor Networks, Senior Software Engineer Feb. 2002–Dec.2005 (Consulting), Dec. 2005–Sep. 2006
Manager: Doug Orr—Vice President, Engineering

• Responsible for optimization of packet capture for network analysis products.
• Implemented drivers for various network adapters and RAID controllers in OpenBSD.

University of Michigan, Research Assistant Jan 2000–Dec 2005
Advisor: Dr. Steven K. Reinhardt—Advanced Computer Architecture Lab

• Research in computer architecture with a focus on improving system architecture for operating systems and networking. This work focuses on improving the performance of TCP/IP networking in general purpose computer systems.
• Key developer of the M5 simulator, a publicly available system-level architecture and processor microarchitecture simulator.
• Built and maintained a network of 100+ Linux workstations used by ACAL students and faculty for experimentation.

Compaq Computer Corporation, Student Intern May–Dec 1999, May–Aug 2000, May–Aug 2001
Supervisor: Dr. Joel S. Emer—VSSAD Research Group

• Helped design and implement ASIM, a timing simulator initially designed for future Alpha processors. The simulator was written in C++ and work involved refining interfaces for simple plug-in of new architectural features. It hast since become one of the primary simulators in use at Intel.
• Worked on a team designing a future generation of Alpha processor. Work involved performance modeling, architectural design, and feasibility of this design.
• Started a group looking into the performance of cryptographic algorithms on Alpha processors investigating the potential gains that could be made through Architectural changes.

University of Michigan, Research Assistant Jan 1999–Apr 1999
Advisor: Dr. Farnam Jahanian—Software Systems Research Lab

• Worked on a project to do performance testing and validation of routing protocols and routing protocol implementations.

University of Michigan, Teaching Assistant Sep 1998–Dec 1998
Instructor: Dr. Steven K. Reinhardt—Electrical Engineering & Computer Science

• Teaching assistant for EECS 373, the design of microprocessor based systems.
• Course covers interfacing microprocessors with hardware where the students concentrate on learning how to design hardware and software that can interact together. Hardware designs had to deal with issues such as properly speaking the microprocessor bus protocol and the software had to deal with issues such as memory mapped I/O and simple device drivers.
• Responsible for teaching two lab sections, writing labs, and writing exam questions.

Intel Corporation, Summer Intern May 1998–Sep 1998
Supervisor: Alex Henstrom—Performance Microprocessor Divison (Pentium 4)

• Logic verification of high-speed domino-like circuitry. Responsible for verifying that the HUL description of circuits matched the transistor schematic of the circuit.
• Wrote a tool that grouped netlist names to simplify a mapping step in the verification. The tool was integrated into the overall design flow to save development time.

SOFTWARE EXPERIENCE

The M5 Simulator 2000–Present
I am a principle developer of the M5 simulator. M5 is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture. My contributions to M5 include the implementation of:

• platform support, enabling a variety of operating systems to be booted within M5;
• detailed I/O and networking subsystems;
• sophisticated statistics gathering framework with automatic generation of graphs;
• pervasive debugging support;
• fully programmable configuration files that are aware of their use in batch queueing;
• checkpointing support.

OpenBSD 2000–Present
OpenBSD is a freely available open source operating system focusing on security. My role as an OpenBSD developer focused on device driver support for Gigabit Ethernet adapters, RAID controllers, and USB devices. In addition, I was involved in support for the Alpha platform.

The LangTech Parser 1994–1997
I developed a natural language parser for English syntax based on residential grammar theory. The parser accepts an English sentence and produces a residential grammar parse tree. This software is currently used for teaching students English syntax and parsing.

AWARDS, GRANTS, & SCHOLARSHIPS

SERVICE & LEADERSHIP

MISCELLANEOUS