Kai-hui Chang

[Chinese Version]

Personal Information:

  • My picture
  • Hometown: Tungshih, Taiwan
  • Birthday: Dec 10, 1976
  • My favorite webpages(designed by me!): Hakka Cuisine, Introductions of Hakka Music, Hakka Clothing
  • My resume

    • Skills:

    Languages:

  • Chinese(Madarin, Hakka, Holo, Cantonese)
  • English
  • Japanese

    • Computer:

  • Homepage design
  • Logo, Basic, Pascal, C, C++, Perl, Verilog, x86 Assembly language
  • Delphi and MFC programming
  • UNIX systems

    • Education:

  • Ph. D., University of Michigan at Ann Arbor, major in Computer Science and Engineering, advisors: Igor Markov, Valeria Bertacco
  • Master, Department of VLSI/CAD, Graduate Institute of Electrical Engineering, advisor: Sy-yen Kuo
  • Bachelor, National Taiwan University Department of Electrical Engineering, graduated at the 3rd place
  • Chien-kuo Senior High School
  • Tun-hwa Junior High School(Second and third grade)
  • Jen-ai Junior High School(First grade)
  • Jen-ai Elementary School

    • Experiences:

  • Avery Design Systems, Senior Technical Staff, 2008/1-present
  • University of Michigan, Post-Doctoral, 2007/9-2007/11
  • Avery Design Systems, project manager, 2003/7-2004/8
  • Avery Design Systems, software engineer, 2001/9-2003/6
  • ALi, summer intern, 1999/7-1999/9
  • Leader of computer department in NTU Hakka Club
  • Designer of Homepages of National Taiwan University Hakka Club
  • Leader of Information Club in Chien-kuo Senior High School
  • System operator of Fantastic Zone BBS

    Awards and Honors

  • 2nd place at ICCAD CADathlon, 2006, see EE Times and CADathlon website
  • 1st place at the Intl. Workshop on Logic and Synthesis (IWLS) Implementation Challenge, 2006, see EETimes
  • Participated in ICCAD CADathlon representing University of Michigan, 2004
  • Awarded in IC/CAD Programming Contest, Taiwan, 2000, 2001
  • Awarded in the Internet Creativity Contest, 1999, 2000
  • HP Homepage Contest 3rd place, 1998
  • Awarded in Homepage Contest held by Ministry of Education of Taiwan, 1997
  • 3rd place in the contest of information of Taiwan, 1995
  • 1st place in the contest of information of Taipei, 1994
  • New Zealand science fair exhibitor's award, 1994
  • Information Olympia camp of Taiwan, 1994
  • 1st place in the contest of Earth Science of Taiwan, 1994
  • 1st place in the contest of Earth Science of Taipei, 1993

    Scholarships

  • Presidential Award, 4 times in college
  • Lung-shan Temple Scholarship, 1997
  • Pan Wen-yuan Scholarship, 1996, 1998

    Publications

    In EDA

    Thesis

  • K. H. Chang, "Functional Design Error Diagnosis, Correction and Layout Repair of Digital Circuits," Ph. D. Thesis, 2007 (Won EDAA Outstanding Dissertation Award at DATE'08 and ACM SIGDA Outstanding Dissertation Award at DAC'09)
  • K. H. Chang, "A Compiled-code Technique for RTL Designs," M. S. Thesis, 2001

    Book

    1. K. H. Chang, I. L. Markov, V. Bertacco, "Functional Design Errors in Digital Circuits: Diagnosis, Correction and Repair", Springer 2009. (ISBN: 978-1-4020-9364-7), Order from Amazon

    Journals

    1. K. H. Chang, D. A. Papa, I. L. Markov, V. Bertacco, "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization", IEEE Design and Test of Computers, vol. 26, no. 2, Mar 2009, pp. 34-43
    2. K. H. Chang, I. L. Markov and V. Bertacco, "Automating Post-Silicon Debugging and Repair", IEEE Computer, vol. 41, no. 7, Jul. 2008, pp. 47-54.
    3. K. H. Chang, I. L. Markov, V. Bertacco, "SafeResynth: A New Technique for Physical Synthesis", Integration: the VLSI Journal, Jul. 2008, pp. 544-556.
    4. K. H. Chang, I. L. Markov, V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis," IEEE Trans. on Computer-Aided Design, Jan. 2008, pp. 184-188.
    5. K. H. Chang, I. L. Markov and V. Bertacco, "Post-placement Rewiring by Exhaustive Search for Functional Symmetries," ACM Transactions on Design Automation of Electronic Systems, Vol. 12, No. 3, Article 32, Aug. 2007.
    6. K. H. Chang, V. Bertacco and I. L. Markov, "Simulation-based Bug Trace Minimization with BMC-based Refinement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 1, Jan. 2007, pp. 152-165.

    Conferences with Proceedings

    1. H. Z. Chou, K. H. Chang and S. Y. Kuo, "Handling Don't-Care Conditions in High-Level Synthesis and Application for Reducing Initialized Registers", to appear in Design Automation Conference (DAC), July 2009
    2. H. Z. Chou, I. H. Lin, C. S. Yang, K. H. Chang and S. Y. Kuo, "Enhancing Bug Hunting Using High-Level Symbolic Simulation", Great Lakes Symp. on VLSI (GLSVLSI), May 2009, pp. 417-420.
    3. K. H. Chang, V. Bertacco, I. L. Markov, "Customizing IP Cores for System-on-Chip Designs Using Extensive External Don't-Cares", Proc. Design Autom. and Test in Europe (DATE), April 2009, pp. 582-585.
    4. K. H. Chang, I. L. Markov, and V. Bertacco, "Reap What You Sow: Spare Cells for Post-Silicon Metal Fix", Int'l Symposium on Physical Design (ISPD), Portland, OR, 2008, pp. 103-110.
    5. K. H. Chang, I. Wagner, V. Bertacco, and I. L. Markov, "Automatic Error Diagnosis and Correction for RTL Designs", IEEE Int'l High Level Design Validation and Test Workshop (HLDVT), Irvine, CA, Nov. 2007, pp. 65-72.
    6. K. H. Chang, I.L. Markov and V. Bertacco, "Automating Post-Silicon Debugging and Repair," Proc. Int'l Conf. on Computer-Aided Design (ICCAD), San Jose, CA, November 2007, pp. 91-98
    7. K. H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization", Proc. Int'l Symposium on Quality Electronic Design (ISQED) San Jose, CA, March 2007, pp. 487-492
    8. K. H. Chang, I. L. Markov and V. Bertacco, "Safe Delay Optimization for Physical Synthesis", Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 628-633
    9. S. Plaza, K. H. Chang, I. L. Markov and V. Bertacco, "Node Mergers in the Presence of Don't Cares", in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 414-419
    10. K. H. Chang, I. L. Markov and V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis", in Proc. Asia and South Pacific Design Automation Conf. (ASPDAC), Yokohama, Japan, January 2007, pp. 944-949
    11. K. H. Chang, I. L. Markov and V. Bertacco, "Post-Placement Rewiring and Rebuffering by Exhaustive Search For Functional Symmetries," Proc. Int'l Conf. Computer-Aided Design (ICCAD), 2005, pp. 56-63
    12. K. H. Chang, V. Bertacco and I. L. Markov, "Simulation-based Bug Trace Minimization with BMC-based Refinement," Proc. Int'l Conf. Computer-Aided Design (ICCAD), 2005, pp. 1045-1051
    13. K. H. Chang, J. Y. Kang, H. W. Wang, W. T. Tu, Y. J. Yeh and S. Y. Kuo, "Automatic Partitioner for Behavior Level Distributed Logic Simulation," Proc. Int'l Conf. Formal Techniques for Networked and Distributed Systems (FORTE), Oct. 2005, Taipei, Taiwan, LNCS 3731, pp 525-528
    14. K. H. Chang, W. T. Tu, H. W. Wang, Y. J. Yeh, and S. Y. Kuo, "Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation," Proceedings of the 16th IASTED International Conference on Parallel and Distributed Computing and Systems(PDCS'04), November 2004, Cambridge, MA, USA
    15. K. H. Chang, W. T. Tu, Y. J. Yeh, and S. Y. Kuo, "A Temporal Assertion Extension to Verilog," Proceedings of the 2nd International Symposium on Automated Technology for Verification and Analysis(ATVA04), October 2004, Taipei, Taiwan, LNCS 3299, pp 499-504
    16. C. C, Yu, K. H. Chang, Y. J. Yeh, and S. Y. Kuo, "System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express," VLSI Design/CAD Symposium, Taiwan, 2004
    17. K. H. Chang, H. W. Wang, Y. J. Yeh, and S. Y. Kuo, "Automatic Partitioner for Distributed Parallel Logic Simulation," IASTED International Conference on Modelling, Simulation and Optimization(MSO'04), Kauai, Hawaii, USA, 2004
    18. K. H. Chang, W. T. Tu, Y. J. Yeh, and S. Y. Kuo, "A Tag-Augmented Temporal Logic Checker," VLSI Design/CAD Symposium, Taiwan, 2003
    19. K. H. Chang, Y. C. Su, W. T. Tu, Y. J. Yeh, and S. Y. Kuo, "A PCI-X Verification Environment Using C and Verilog," VLSI Design/CAD Symposium, Taiwan, 2003
    20. Y. J. Yeh, K. H Chang, M. T. Chen, and S. Y. Kuo, "Compiled-code Technique for RTL Designs," VLSI Design/CAD Symposium, Taiwan, 2001

    Conferences without Proceedings/Posters/Other

    1. K. H. Chang, V. Bertacco, I. L. Markov, and A. Mishchenko, "Synthesis with External Don't-Cares Using Shannon Entropy and Craig Interpolation", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Lake Tahoe, CA, 2008
    2. K. H. Chang, I. Wagner, V. Bertacco, and I. L. Markov, "Automatic Error Diagnosis and Correction for RTL Designs", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 106-113.
    3. K. H. Chang, I. L. Markov, and V. Bertacco, "Automating Post-Silicon Debugging and Repair", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 114-121.
    4. K. H. Chang, I. L. Markov, and V. Bertacco, "Fast Verification of Retiming", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), San Diego, CA, May 2007, pp. 165-166.
    5. K. H. Chang, D. A. Papa, I. L. Markov and V. Bertacco, "Fast Simulation and Equivalence Checking Using OAGear", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Denver, CO, June 2006, pp. 270-271.
    6. K. H. Chang, I. L. Markov and V. Bertacco, "Keeping Physical Synthesis Safe and Sound", ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Denver, CO, June 2006, pp. 86-93.
    7. K. H. Chang, J. Y. Kang, C. L. Huang, J. P. Hayes and I. L. Markov, "Fast Test Simulation via Distributed Computing," Technical paper, Avery Design Systems, 2006
    8. K. H. Chang, I. L. Markov and V. Bertacco, "Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries," ACM/IEEE Int'l Workshop on Logic and Synthesis (IWLS), Lake Arrowhead, CA, June 2005, pp. 469-476.
    9. K. H. Chang, W. T. Tu, Y. J. Yeh, and S. Y. Kuo, "A Simulation-Based Temporal Assertion Checker for PSL," IEEE International Midwest Symposium on Circuits and Systems(MWSCAS'03), Cairo, Egypt, 2003

    Patents

    1. K. H. Chang, I. Wagner, V. Bertacco, and I. L. Markov,"Automatic Error Diagnosis and Correction for RTL Designs", United States Patent Application 20080295043, November 27, 2008

    In Lingustics/Computational Lingustics/Other

    Journals

    1. K. H. Chang, J. T. Fan, and S. Y. Kuo, "Design and Implementation of Mandarin-to-Hakka Translation and Speech Synthesis System," Center for Hakka Studies Newsletter, issue 7, Hakka Research Center, National Central University, 2005, pp 152-168.
    2. K. H. Chang, J. T. Fan, and S. Y. Kuo, "A Talking Browser," Journal of Internet Technology, July 2001, pp 171-176
    3. K. H. Chang, "Relationship between Hakka, Mandarin and Japanese Kanji and Its Application," Journal of Taiwan Language and Language Education Vol. 2, National Hsin-chu Teachers College, 2000, pp 79-90
    4. K. H. Chang, "Implementation and Analysis of Remote Home Appliances and Security System," Communications of IICM, June 1999
    5. K. H. Chang, "The Way to Use Other Languages to Aid the Study of Hakka Dialect," Hakka Magazine, June 1999
    6. K. H. Chang, "Hakka Diactionary and Hakka Input Method," Hakka Magazine, October 1997
    Email address:changkh@umich.edu