Intel IA-32 (x86) architecture memory management:

  (summarized and simplified from:  Intel Architecture Software
  Developer's Manual Volume 3: System Programming Guide)

  This information is generally applicable for the 386 and
  all higher models of the Intel x86 32 bit architecture.

  The IA-32 uses both segmentation and paging; logical
  addresses first go through a segmentation mechanism to
  produce a 32 bit "linear" address, then this goes through
  a paging mechanism to produce a physical address.

  Segmentation:

    The processor has 6 segment registers, named:
      CS
      SS
      DS
      ES
      FS
      GS
    Instruction fetches always use CS (code segment)
    Stack references use SS (stack segment)
    Other data references generally use DS (data segment)
    but instructions can explicitly request another segment
    (such as ES, FS, or GS) instead.

    Segment registers are 16 bits:
       2 bits involved in privilege level
       1 bit to choose local or global descriptor table
      13 bits to choose one of the 8K descriptor table entries

      The descriptor table contains base and limit for the segment.
        The base is a normal 32 bit address.
        The limit is 20 bits, a mode bit allows it to be used as either:
          1 byte to 1 MBytes, in 1 byte increments
          4 KBytes to 4 GBytes, in 4 KByte increments
        The descriptor table entry also contains protection information

      The global descriptor table resides in physical memory;
      dedicated register (GDTR) gives base and limit for this table.
      The global descriptor table MUST be used; the local descriptor
      table is optional.  If LDT is used, one of the segments
      described in the GDT may be used as a local descriptor table.

      The appropriate segment descriptors are always copied 
      into one of 6 dedicated register areas whenever any of the
      6 segment registers are modified; thus, the descriptor
      tables are normally accessed infrequently.
      
    There is no provision in hardware for disabling segmentation.

    The result of all this so far is a 32 bit linear address.

  Paging:

    Normally, the 32 bit linear address space is broken into 4 KByte
    pages, although paging may be disabled altogether.  Some CPU
    models support an alternative huge page size (2 of 4 MBytes);
    this is apparently not used in most applications.

    The page table mechanism is a straightforward two-level scheme.
    A dedicated register (control register 3) is the page directory
    base register.  This points to a page directory.  The top 10 bits
    (bits 31 through 22) of the linear address are used to index into
    the page directory.  The page directory entry specifies the base
    address of the page table, and the next 10 bits (bits 21 through 12)
    of the linear address are used to index into the page table.
    The page table entry specifies a physical page, and the bottom
    12 bits (bits 11 through 0) of the linear address are used
    as the offset within the page.  Page table and and page directory
    entries are 4 bytes long, and the tables contain 1K entries each,
    so these tables each occupy exactly one 4K page.

    Some models (Pentium Pro, Pentium II, and presumably all forthcoming
    newer models) provide a mechanism to increase the physical address
    space from 32 to 36 bits.  This is done with the following changes:

       All page table and page directory entries from 32 to 64 bits, to
       allow for sufficiently large pointers.  The sizes remain at one
       4 KByte page per table, so each table can now only hold 512
       entries, so only 9 bits of linear address are used to index into
       these structures.

       A third level is added at the top of the table hierarchy;
       the page directory pointer table, with 4 entries of 64
       bits each.

       CR3 is padded with zeros at the low end to form the base
       address for the page directory pointer table.

       In summary, the bits in this mode are translated as follows:

         31 - 30    index into page directory pointer table
         29 - 21    index into page directory
         20 - 12    index into page table
         11 -  0    offset in page

  TLB:

    All current processor models use a TLB, but the size
    varies by model and models may also differ as to whether
    they use a single TLB or separate code/data TLB's.

Practical applications:

  Many (most?) OS's for the x86 architecture do not make any use of the
  segmentation.  They just define a single global segment that spans the
  full 32 address space and set all segment registers to refer to this
  segment.  Linux may use one extra segment when in certain kernel calls
  as a means of accessing user space without needing any pointer
  manipulation.  I am not aware of any OS's that use the 36 bit physical
  address mode.  For one thing, it is not needed until physical memory
  exceeds 4 GB, and current x86 support chipsets generally do not
  allow more than 2 GB in a system.

  Thus, the OS software just manages a conventional two level paging
  scheme with a 4K page size.