Ilya Wagner
Ph.D. student | Current CV
Advanced Computer Architecture Lab
Department of Electrical Engineering and Computer Science
Colledge of Engineering
University of Michigan
Ph.D. Computer Science and Engineering ' 08 University of Michigan
M.S.E in Computer Engineering ' 06 University of Michigan
B.S.E in Computer Engineering ' 04 (Summa Cum Laude), University of Michigan
Advisors:
Office: CSE 2765
Dissertation Title:
An Effective Verification Solution for Modern Microprocessors
Research:
Reversi: Post-silicon Validation System for Modern Microprocessors
Today, post-silicon verification is often deployed to detect complex functional bugs in microprocessors in addition to exposing electrical and manufacturing defects. This is due to the significantly higher execution performance offered by post-silicon techniques compared to pre-silicon methods. Validation at post-silicon level is carried out primarily by executing constrained-random tests directly on the prototype hardware. However, to identify errors, the state obtained from executing randomized tests on the prototype must be compared to the one produced by an architectural simulation of design's golden model, thereby limiting the overall performance of the validation effort. In our work we propose Reversi, a framework designed to address the simulation bottleneck of the traditional post-silicon verification flow. Reversi generates random programs in such a way that their correct final state is known at generation time, eliminating the need for costly architectural simulation. Our experimental results show that Reversi generates tests exposing more bugs faster, and can speed up post-silicon validation by twenty times compared to traditional flows.
MCjammer: An Adaptive Verification Tool for Multi-core and Multi-processor Designs
The challenge of verification of multi-core and multi-processor designs grows dramatically with each new generation of systems produced today. Validation of memory coherence and memory consistency of the entire system, which includes multiple level of cache and complex protocols, remains a major fraction of this difficult task. In our work we present a scalable approach to verification of memory coherence and consistency protocols called MCjammer. MCjammer framework features multiple cooperating agents, each assigned to individual processor core. Agents feature an abstract representation of the entire system that allows them to efficiently collaborate and create complex testing sequences stressing the memory sub-system of the design and expose complex coherence and consistency errors. Our experiments demonstrate that MCjammer is capable of reaching significantly higher levels of full system FSM coverage much faster than traditional constrained-random approaches.
Engineering Trust with Semantic Guardians
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trusted systems. Unfortunately, this goal remains an unfulfilled challenge today, as majority of the designs are released with latent bugs. Patching techniques can repair some of these escaped erros, however, they can be invoked only after the bug has been exposed at the customer site. Semantic guardian framework is a novel approach to guaranteeing correct system operation even in presence of unknown escaped errors. A semantic guardian is implemented as an additional control logic block, which ensures that the design always operates in a verified state. The experimental results demostrate that a guardian block can occupy less than 3.5% area of a processor and incur as little as 5% performance overhead.
Shielding Against Design Flaws with Field Repairable Control Logic
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs that escape into silicon will only grow in the future. We propose a novel hardware patching mechanism that can detect design errors which escaped the verification process, and can correct them directly in the field. We accomplish this goal through a simple fieldprogrammable state matcher, which can identify erroneous configurations in the processor's control state and switch the processor into formally-verified degraded performance mode, once a "match" occurs. When the instructions exposing the design flaw are committed, the processor is switched back to normal mode. We show that our approach can detect and correct infrequently-occurring errors with almost no performance impact and has approximately 2% area overhead. In our recent extension of FRCL we investigate the applicability of this approach to memory sub-system patching in multi-core processors.
IQTest: Depth-Driven Verification of Simultaneous Interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This trend is accelerated with the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces. In this work, we introduce a closed-loop feedback technique targeting the verification of multiple components connected by parallel interfaces. We utilize an environment with hierarchical Markov models, where top-level submodels specify overarching simulation goals of the system, while lower-level submodels specify the detailed component-level input generation. Test accuracy is improved through the use of depth-driven random test generation. The approach allows users to specify correctness properties and key activity nodes in the design to be exercises. We examine three non-trivial designs, two microprocessors and a chip-multiprocessor router switch, and we demonstrate that our technique finds many more bugs than constrained-random test generation technique and reduces the simulation effort in half, compared to previous Markov-model based solutions.
StressTest
StressTest is a directed-random test generator for hardware verification. It consists of a Markov-model random instruction generator and activity monitors. The model is generated from the user specified template programs and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity points within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov model into one that effectively stresses the points of interest. In parallel, StressTest monitors the correctness of the DUT response to the supplied stimuli, and if the design behaves unexpectedly, a bug and a trace that leads to it are reported.
Course Projects:
EECS 427. VLSI Design (Winter 06): Report
EECS 570. Parallel Computer Architecture (Fall 04): Report
EECS 578. CAD and Verification of Digital Systems (Winter 05): Report
EECS 590. Grad. Programming Languages (Winter 05): Report
Activities:
Michigan Mars Rover Design Project
Publications:
Andrew DeOrio, Ilya Wagner and Valeria Bertacco,"Dacota: Post-Silicon Validation of the Memory Subsystem in Multi-core designs". International Symposium on High Performance Computer Architecture 2009
Joseph Greathouse, Ilya Wagner, David Ramos, Gautam Bhatnagar, Todd Austin, Valeria Bertacco and Seth Pettie,"Testudo: Heavyweight Security Analysis via Statistical Sampling". International Symposium on Microarchitecture 2008
Ilya Wagner and Valeria Bertacco,"Reversi: Post-Silicon Validation System for Modern Microprocessors". International Conference on Computer Design 2008 (Best paper award)
Ilya Wagner and Valeria Bertacco, "MCjammer: An Adaptive Verification Tool for Multi-core and Multi-processor Designs". Design, Automation and Test in Europe 2008
Ilya Wagner, Valeria Bertacco, Todd Austin, "Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors". IEEE Transactions on Computer-Aided Design February 2008
Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor Markov, "Automatic Error Diagnosis and Correction for RTL Designs". High Level Design Validation and Test Workshop 2007
Ilya Wagner and Valeria Bertacco, "MCjammer: An Adaptive Verification Tool for Multi-core and Multi-processor Designs". International Workshop on Logic and Synthesis 2007
Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor Markov, "Automatic Error Diagnosis and Correction for RTL Designs". International Workshop on Logic and Synthesis 2007
Ilya Wagner, Valeria Bertacco, Todd Austin. "Microprocessor Verification via Feedback-Adjusted Markov Models". IEEE Transactions on Computer-Aided Design June 2007
Ilya Wagner, Valeria Bertacco, "Engineering Trust with Semantic Guardians". Design, Automation and Test in Europe 2007
Ilya Wagner, Valeria Bertacco, Todd Austin, "Shielding Against Design Flaws with Field Repairable Control Logic". Design Automation Conference 2006. Available here.
Ilya Wagner, Valeria Bertacco, Todd Austin, "Depth-Driven Verification of Simultaneous Interfaces". Asian-South Pacific Design Automation Conference 2006. Available here.
Halil Hamut, Christine Kryscio, Eric Nytko, Jarrod Rivituso, Chad Rowland, Frantisek Sobolic, Matthew Van Kirk, Anna Paulson, Ilya Wagner "Universal Chassis for Modular Ground Vehicles". Revolutionary Aerospace Systems Concepts - Academic Linkage (RASC-AL) Forum 2005. http://marsrover.engin.umich.edu/RASC-AL/RASC-AL_Report.pdf
Ilya Wagner, Valeria Bertacco, Todd Austin, "StressTest: An Automatic Approach to Test Generation Via Activity Monitors". Design Automation Conference 2005. Available here.
Chad Rowland, Anna Paulson, Ilya Wagner, William Green, James Beyer "Surface Mobility Technology Development: Pressurized Mars Rovers," University of Michigan, 2004. http://marsrover.engin.umich.edu/projects/research_reports_2004/SurfaceMobility.pdf
Jim Beyer, Matt Van Kirk, Tom Lau, Eric Nytko, Christian Passow, Fritz Passow, Boyang Tang, Ilya Wagner, "Sampling Systems Evaluation Software" http://marsrover.engin.umich.edu/projects/research_reports_2004/Sampling_Report.pdf
Anton VanderWyst, Ilya Wagner, Reza Farsain "Olympus Radiation Shielding" http://marsrover.engin.umich.edu/projects/research_reports_2003/RadiationEffects.pdf
Yep, that's me:
