Marios C. Papaefthymiou - Select Publications

• Low-energy design
• Timing analysis and optimization
• Parallel and distributed computing

Low-energy design

• S. Kim and M.C. Papaefthymiou. Reconfigurable low energy multiplier for multimedia system design . In IEEE Annual Workshop on VLSI , April 2000.

• G. Bernacchia and M.C. Papaefthymiou. Analytical macromodeling for high-level power estimation . In Technical Digest of the 1999 IEEE/ACM International Conference on Computer-Aided Design, November 1999.

• S. Kim and M.C. Papaefthymiou. Low-energy adder design with a single-phase source-coupled adiabatic logic . In PATMOS '99, 9th International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.

• S. Hong, S. Kim, M.C. Papaefthymiou, and W.E. Stark. Low power parallel multiplier design for DSP applications through coefficient optimization . In 12th IEEE International ASIC/SOC Conference, September 1999.

• S. Kim and M.C. Papaefthymiou. Single-phase source-coupled adiabatic logic . In International Symposium on Low-Power Electronics and Design, August 1999.

• S. Hong, S. Kim, M.C. Papaefthymiou, and W.E. Stark. Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications . In 42nd Midwest Symposium on Circuits and Systems, August 1999.

• S. Kim and M.C. Papaefthymiou. Pipelined DSP design with a true single-phase energy-recovering logic style . In VOLTA'99 IEEE Alessandro Volta Memorial International Workshop on Low Power Design, March 1999.

• S. Kim and M.C. Papaefthymiou. True single-phase energy-recovering logic for low-power, high-speed VLSI. In 1998 International Symposium on Low-Power Electronics and Design, August 1998.

• K.N. Lalgudi and M.C. Papaefthymiou. Fixed-Phase Retiming for Low Power Design . In 1996 International Symposium on Low Power Electronics and Design, August 1996.

• M.C. Knapp, P.J. Kindlmann, and M.C. Papaefthymiou. Implementing and Evaluating Adiabatic Arithmetic Units . In Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, May 1996.

• M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M.C. Papaefthymiou. Precomputation-Based Sequential Logic Optimization for Low Power . IEEE Transactions on VLSI Systems, Special Issue on Low Power Design, December 1994. Earlier versions of this paper appeared in Technical Digest of Papers of the 1994 IEEE/ACM International Conference on Computer-Aided Design, November 1994, and in 1994 International Symposium on Low Power Design, April 1994.

Timing analysis and optimization

• X. Liu, M.C. Papaefthymiou, and E.G. Friedman. Maximizing performance by retiming and clock skew scheduling . In Proceedings of the 36th ACM/IEEE Design Automation Conference, June 1999.

• X. Liu, M.C. Papaefthymiou, and E.G. Friedman. Minimizing sensitivity to delay variations in high-performance synchronous circuits . In Proceedings of the 1999 IEEE Conference on Design, Automation, and Test in Europe , March 1999.

• M.C. Papaefthymiou. Asymptotically efficient retiming under setup and hold constraints . In Technical Digest of Papers of the 1998 IEEE/ACM International Conference on Computer-Aided Design, November 1998.

• M.C. Papaefthymiou, E.G. Friedman, and X. Liu. Retiming and clock scheduling for high-performance synchronous circuits. In PATMOS '98, Eighth International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1998.

• K.N. Lalgudi, M.C. Papaefthymiou, and M. Potkonjak. Optimizing Computations for Effective Block-Processing. In Proceedings of the 33rd ACM/IEEE Design Automation Conference, June 1996. An extended version of this paper appeared as Technical Report YALEU/DCS/RR-1102, April 1996.

• A.T. Ishii and M.C. Papaefthymiou. Efficient Pipelining of Level-Clocked Circuits with Min-Max Propagation Delays . In TAU'95 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, November 1995.

• K.N. Lalgudi and M.C. Papaefthymiou. Delay: An Efficient Tool for Retiming with Realistic Delay Modeling . In Proceedings of the 32nd ACM/IEEE Design Automation Conference, June 1995. Received Best Paper Award.

• K.N. Lalgudi and M.C. Papaefthymiou. Efficient Retiming under a General Delay Model . In Advanced Research in VLSI: Proceedings of the 1995 Chapel Hill Conference, March 1995.

• M.C. Papaefthymiou and K.H. Randall. TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry . In Proceedings of the 30th ACM/IEEE Design Automation Conference, June 1993.

• M.C. Papaefthymiou and K.H. Randall. Edge-Triggering vs. Two-Phase Level-Clocking . In Research on Integrated Systems: Proceedings of the 1993 Symposium, March 1993.

• A.T. Ishii, C.E. Leiserson, and M.C. Papaefthymiou. Optimizing Two-Phase, Level-Clocked Circuitry . Journal of the ACM, Vol. 44, No. 1, pp. 148--199, January 1997. An extended abstract appeared in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, March 1992.

• M.C. Papaefthymiou. Understanding Retiming through Maximum Average-Delay Cycles . Mathematical Systems Theory, No. 27, pp. 65--84, 1994. An early version of this paper appeared in Proceedings of the 3rd ACM Symposium on Parallel Algorithms and Architectures, July 1991.

Parallel and distributed computing

• F. Wang, M.C. Papaefthymiou, and M.S. Squillante. Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming . In Workshop on Job Scheduling Strategies for Parallel Processing of the 1997 International Parallel Processing Symposium, April 1997.

• M.S. Squillante, F. Wang, and M.C. Papaefthymiou. Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems . In Performance '96, October 1996.

• M.S. Squillante, F. Wang, and M.C. Papaefthymiou. An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. In Proceedings of the 8th ACM Symposium on Parallel Algorithms and Architectures, June 1996.

• F. Wang, H. Franke, M.C. Papaefthymiou, P. Pattnaik, L. Rudolph, and M.S. Squillante. A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. In Workshop on Job Scheduling Strategies for Parallel Processing of the 1996 International Parallel Processing Symposium, April 1996.

• M.C. Papaefthymiou and J. Rodrigue. Implementing Parallel Shortest-Paths Algorithms. In The Third DIMACS International Algorithm Implementation Challenge on Parallel Algorithms , October 1994. Journal version appeared in Parallel Algorithms, S.N. Bhatt (ed.), DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 30, 1997.

• A. Agarwal, J. Guttag, C. Hadjicostis, and M.C. Papaefthymiou. Memory Assignment for Multiprocessor Caches through Grey Coloring . In Parallel Architectures and Languages Europe, July 1994.