Prof. Pinaki Mazumder
Department of Electrical Engineering and Computer Science, University of Michigan

4765 CSE Building, 2260 Howard Avenue, Ann Arbor, MI 48109-2121, USA
mazum@eecs.umich.edu +1 (734) 763-2107 +1 (734) 763-8094


  • Significant Journal Publications

    •  (1) [Double-bit ECC in Giga-bit DRAM Chips],  (2)  [RTD Modeling Technique],   (3) [Full-Chip Thermal Modeling for CMOS],  (4)  [RTD Circuit Design Techniques] ,  (5)  [VLSI Standard Cell Placement Algorithms],  (6)  [Quantum SPICE Simulator],  (7)  [Parallel Parametric Testing of DRAM Chips], (9)  [Optimal Tapering of Transistors in CMOS Circuits], (10)  [VLSI Interconnect Modeling Using Differential Quadrature Method],  (11) [Genetic Algorithm for VLSI Cell Placement],  (12) [Self-Repair Technique for VLSI Chips], (13)  [Self-Repair Technique for VLSI Processor Arrays],   (15) [Self-Repair Technique for Memory Array], (16)  [Parallel Genetic Algorithm for VLSI Cell Placement], (17)  [Parallel Testing of Semiconductor Memories],  (18)  [Built-in Self-Testing of CAM Memories], (19)  [Built-in Self-Repairable Memory Compiler],  (20) [Multivalued Adder Design Using RTD's], (21)  [RTD-based Keeper Design for Domino Logic with Improved Noise Performance], (22)  [RTD-based Low-Power and High-Speed Memory System],  (23) [Evaluation of On-Chip Parallel Processing Circuits] (24)  [VLSI Layout Technique for On-Chip Parallel Processing]  (25)  [Gate Leakage current Modeling for Nanoscale CMOS FET]  (26)  [Crosstalk Noise Modeling in VLSI] [Simultaneous Switching Noise Modeling in VLSI]  (27)  [MVL Boolean Logic Synthesis using RTD Circuits]  (28)  [Unified Wire Routing Algorithms for VLSI Layout]
     Books
    1. Genetic Algorithms for VLSI Design, Layout & Test Automation (Hardcover)
      by Pinaki Mazumder and Elizabeth Rudnick [html] [pdf]
    2. Testing and Testable Design of High-Density Random-Access Memories  (Hardcover) by Pinaki Mazumder and Kanad Chakraborty [html] [pdf]
    3. Fault Tolerance and Reliability Techniques for High-Density Random-Access Memories (Hardcover) by Kanad Chakraborty and Pinaki Mazumder [html] [pdf]
         For other books, see Prof. Mazumder's [Resume].  DRAM Circuits Design
    Intergovernmental Personnel Assignment (IPA)

    Currently serving as Program Director at the National Science Foundation to manage the Emerging Models and Technologies research program, which is with the Division of Computing and Communications Foundations in the Directorate for Computer and Information Science and Engineering.

    NSF e-mail contact address:     pmazumde@nsf.gov
    NSF surface mail address:     Emerging Models and Technologies for Computation Cluster (CISE/CCF), The National Science Foundation, 4201 Wilson Boulevard, Arlington, Virginia 22230, USA.
    Telephone and Fax: Phone: (703) 292-8910 |    Fax: (703) 292-9059 |  Room: 1115 N

    Program Solicitation for EMT: Nanoelectronics, Quantum Computing and Biologically Inspired Computing. [html] [pdf]
    Note that the deadline for full proposal is on February 14, 2007.

  • Invited Talks: [Prof. Mazumder's Presentations]
  • NDR Group: Contact Prof. Mazumder at mazum@eecs.umich.edu for information.
  • Photographs of Prof. Mazumder: [UM Faculty Page] Other Photographs: [P1] [P2], [P3], [P4]
  • Sports Accomplishments: [Tennis Prizes] Sample Tennis Postings [Posting1] [Posting2]
  • Homage: [The Greatest Geniuses]
  • Supplication: [A Nobel Laureate's Vision]
  • Research Assistantships
    • Main Research Accomplishments and Contributions:
  • Industrial R&D Experience
    * Worked over 6 years in industrial R&D laboratories. Designed (1976-82) analog and digital integrated circuits (went into production for over 100 million units). Developed (1985-86) the first C-language based EDA synthesis tool (CONES which was later renamed as SPRUCE) at AT&T Bell Labs, Indian Hill, Chicago.

  • Research Accomplishments in Semiconductor Memories
    * Invented a new testable memory circuit to perform multiple-cell line-mode testing, a method that is now widely used in DRAM chips in order to reduce memory chip testing cost by two orders of magnitude.
    * Proposed layout and process based parallel test algorithms that are now widely used by memory manufacturers in testing giga-bit DRAM and SRAM chips.
    * Studied the mechanism of double-bit errors due to alpha particles striking between trench DRAM cells, and proposed a new on-chip double-bit error correcting circuit that improves memory storage reliability by over one million times.
    * Developed a unified approach to built-in self-repair of VLSI chips by proposing pseudo-analog adaptive self-healing circuits that can perform combinatorial optimization algorithms such as maximum matching and node covering on bipartite graphs in order to substitute the faulty circuit elements by spare elements located at the boundary of the memory/processor array.
    * Developed a built-in self-repairable SRAM compiler that can generate the layout of user-defined technology-independent embedded SRAM and Cache memories along with their VHDL and Verlog models. (100,000 lines of C codes were written).

  • Research Accomplishments in Quantum and Nanoelectronic Circuits and CAD Tools
    * Developed accurate modeling of quantum tunneling current through RTD's using Envelope Function Method and Quantum Dots using Transfer Matrix Method.
    * Developed quantum dot (also RTD+HEMT) based nanoarchitecture for monochronmatic and colr image processing and video motion detection.
    * Developed several new circuit configurations that employ quantum-effect devices to improve speed of circuit operation and to reduce power consumption for III-V compound semiconductor integrated circuits.
    * Developed numerous Quantum MOS circuits that use Silicon and Si-Ge based RITD and CMOS devices to yield better power-delay performance.
    * Developed Quantum SPICE simulator on Berkeley SPICE code to incorporate physics-based device models of a number of quantum-effect devices and homotopy based new convergence routines to circumvent DC and Transient convergence problems encountered while simulating highly nonlinear RTD circuits having multiple DC solutions.
    * Developed Finite Difference Transmission Line Matrix (FDTLM) based full-chip modeling tool for simulating RTD, HBT and HEMT based circuits.
    * Developed SPICE compatible equivalent circuit models for surface plasmon propagation over nano particles and nanoshells (Work in progress for nanowires and nanoholes).

  • Research Accomplishments in Nanoscale CMOS Systems Design
    * Developed Schrödinger and Poisson equations solver to unifiedly model leakage currents in gate dielectrics of nanoscale CMOS devices.
    * Developed optimal tapering of FET chains in high-speed CMOS circuits.
    * Developed Differential Quadrature Method based interconnect modeling techniques and combined the wiring model with Quantum SPICE.
    * Developed Finite Difference Quadrature Method for modeling the signal integrity in a VLSI chip in presence of electromagnetic waves emanated from on-chip and external sources
    * Developed multi-layer Green's function based accelerated chip-level thermal analysis including ambient temperature effects
    * Developed simultaneous switching, coupling, and dynamic noise modeling techniques for VLSI chips and designed new noise-aware CMOS circuit design techniques.

  • Research Accomplishments in VLSI Layouts 
    * Developed a suite of distributed layout tools to demonstrate capabilities of Genetic Algorithms for solving placement, partitioning, floor-planning, and routing problems on a network of workstations.
    * Developed a suite of layout critique tools that can automatically optimize a finished layout to reduce manufacturing defects occurring randomly at various process steps.
    * Developed a unified parallel VLSI chip routing method by using an ensemble of polymorphic processing elements which can improve the speed by an order of magnitude for a wide class of chip routing styles like maze, channel, switch-box, area, and so on.
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    Last Updated on December 10, 2006