Mojtaba Mehrara

Advanced Computer Architecture Lab.
EECS department, 2260 Hayward St.
Ann Arbor, MI 48105

RESEARCH INTERESTS

My research interests lie in the area of compilers and computer architecture. I am mainly interested in compiler and architecture techniques for improving programmability and usability of parallel systems.

EDUCATION

2007-present

University of Michigan

Ann Arbor, MI

PhD. Candidate - Computer Science and Engineering

Advisor: Prof. Scott Mahlke

2005-2007

University of Michigan

Ann Arbor, MI

M.S.E - Computer Science and Engineering

GPA: 8.5/9.0 (A=8.0, A+=9.0)

2001-2005

Sharif University of Technology

Tehran, Iran

B.S - Electrical Engineering

GPA: 17.2/20.0

PUBLICATIONS

PLDI'09

Parallelizing Sequential Applications on Commodity Hardware using a Low-cost Software Transactional Memory

Mojtaba Mehrara, Jeff Hao, Po-Chun Hsu, and Scott Mahlke

To appear in the ACM SIGPLAN 2009 Conference on Programming Language Design and Implementation (PLDI'09) , June 2009

PPoPP'09

Transactional Memory with Strong Atomicity using Off-the-shelf Memory Protection Hardware

Martin Abadi, Tim Harris, and Mojtaba Mehrara

In Proc. of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'09) , pp. 185 - 196, Feb 2009

TACO'08

Exploiting Selective Placement for Low-cost Memory Protection

Mojtaba Mehrara, and Todd Austin

In the ACM Transactions on Architecture and Code Optimization , Vol. 5, Issue 3, Article 14, Nov 2008

HPCA'08

Uncovering Hidden Loop-Level Parallelism in Sequential Applications

Hongtao Zhong, Mojtaba Mehrara, Steven Lieberman, and Scott Mahlke

In Proc. of the 14th International Symposium on High-Performance Computer Architecture (HPCA'08) , pp. 290 - 301, Feb 2008

ISCA'07

Architectural Implications of Brick and Mortar Silicon Manufacturing

Martha Mercaldi, Mojtaba Mehrara, Todd Austin, and Mark Oskin

In Proc. of the 34th International Symposium on Computer Architecture (ISCA’07) , pp. 244 - 253, June 2007

DATE'07

Low-cost Protection for SER Upsets and Silicon Defects

Mojtaba Mehrara, Mona Attariyan, Smitha Shyam, Kypros Constantinides, Valeria Bertacco, and Todd Austin

In Proc. of the conference on Design, Automation and Test in Europe (DATE’07) , pp. 1146 - 1151, April 2007

MSPC'06

Reliability-Aware Data Placement for Partial Memory Protection in Embedded Processors

Mojtaba Mehrara, and Todd Austin

In Proc. of the 2006 ACM SIGPLAN Workshop on Memory System Performance and Correctness (MSPC'06) , pp. 11 - 18, October 2006

IEE'05

Reduced Complexity 1-bit High-order Digital Delta-Sigma Modulator for Low-voltage Fractional-N Frequency Synthesis Applications

Babak Bornoosh, Ali Afzali-Kusha, Reza Dehghani, Mojtaba Mehrara, and M. Nourani

In the IEE Proceedings on Circuits, Devices and Systems , Vol. 152, Issue 5, pp. 471 - 477, October 2005

WORK EXPERIENCE

Jan. 2006 - present

University of Michigan

Ann Arbor, MI

Advanced Computer Architecture Lab.

Graduate Student Research Assistant

June 2008 - Sept. 2008

Microsoft Research

Cambridge, UK

Manager: Dr. Tim Harris

Research Intern

Worked on providing strong atomicity to Bartok-STM using the memory protection hardware

March 2005 - June 2005

Pardis Novel Processing Technology Co.

Tehran, Iran

R&D Engineer (part-time)

Designed and implemented a Turbo decoder using the SOVA algorithm on FPGA. This core is now part of the company's IP core library.

Sept. 2003 - Nov. 2004

Resana Afzar Sharif Co. Ltd.

Tehran, Iran

R&D Engineer (part-time)

Designed and implemented a data-logger on FPGA using SDRAM with a USB interface. Data-logger is now being sold as a product by the company.

HONORS and AWARDS

2005

Awarded the University of Michigan EECS Department graduate fellowship

2005

Awarded the University of Michigan EECS Department five-year guaranteed graduate funding

2001

Ranked 1st among 400,000 participants in Azad University entrance exam, Iran

2001

Ranked 9th among 350,000 participants in the nationwide university entrance exam, Iran

GRADUATE COURSES

EECS 523

Digital Integrated Circuit Technology

SERVICE

Web Chair:

2008 Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA'08), Bejing, China, June 2008

Reviewer:

International Symposium on Computer Architecture (ISCA'07, ISCA'08)
International Conference on Microarchitecture (MICRO'07)
International Symposium on High-Performance Computer Architecture (HPCA'08)
International Symposium on Code Generation and Optimization (CGO'08)
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'09)
Design Automation and Test in Europe (DATE'07)

Mojtaba Mehrara

RESEARCH INTERESTS

EDUCATION

University of Michigan

University of Michigan

Sharif University of Technology

PUBLICATIONS

Parallelizing Sequential Applications on Commodity Hardware using a Low-cost Software Transactional Memory

Transactional Memory with Strong Atomicity using Off-the-shelf Memory Protection Hardware

Exploiting Selective Placement for Low-cost Memory Protection

Uncovering Hidden Loop-Level Parallelism in Sequential Applications

Architectural Implications of Brick and Mortar Silicon Manufacturing

Low-cost Protection for SER Upsets and Silicon Defects

Reliability-Aware Data Placement for Partial Memory Protection in Embedded Processors

Reduced Complexity 1-bit High-order Digital Delta-Sigma Modulator for Low-voltage Fractional-N Frequency Synthesis Applications

WORK EXPERIENCE

University of Michigan

Microsoft Research

Pardis Novel Processing Technology Co.

Resana Afzar Sharif Co. Ltd.

HONORS and AWARDS

GRADUATE COURSES

Advanced Compilers

Parallel Computer Architecture

Computer Architecture

VLSI Design I

Microarchitecture

Digital Integrated Circuit Technology

Design and Analysis of Algorithms

Artificial Intelligence

SERVICE