About Me

I am a second year PhD student in the EECS program at The University of Michigan, Ann Arbor. I am working with Professor Thomas Wenisch in the Advanced Computer Architecture Lab (ACAL). My research focuses on energy efficiency in large scale data centers, multi-core computer architecture and virtualization.

I earned my ScB in Electrical Engineering at Brown University in Providence, RI. There I worked with Sherief Reda in the Scalable Computing Systems Laboratory (SCALE).

Research Interests

Energy Efficient Data Centers

I am the lead student researcher for PowerNap [ASPLOS 09] a server architecture which eliminates idle power. In observed deployments, these servers can save as much as 74% of a server's energy usage. PowerNap operates by transitioning rapidly between a high-performance active state during periods of work and a coordinated low-power nap state while idle. This architecture provides greater power savings than other power management techniques such as DVFS while incurring negligible performance overhead.

Because PowerNap servers exhibit unique power requirements, we have developed RAILS, the Redundant Array for Inexpensive Load Sharing. Analogous to RAID, our PSU provisioning methodology links together numerous small, commodity parts. This provides more efficient power conversion than currently available products in the enterprise space. Furthermore, RAILS is cheaper than currently available systems and lends itself to graceful degradation.

Hardware Acceleration for Multi-Core Architectures

Multi-core architectures and parallel systems are demanding a reevaluation of chip design. Specifically, I look at prototyping these systems quickly in reconfigurable logic for rapid analysis. I investigate reducing "bloat" in terms of logic, chip area and power consumption frequently created when multiple cores are replicated on a single die.

At Brown University, I helped develop Hardware Libraries [ICCD 07], an architecture that efficiently distributes hardware accelerators among multiple cores. Many important applications (e.g. DNA sequencing, image processing) require hardware acceleration. However, since utilization of these units can be sparse, these resources can be multiplexed among many CPU cores. This allows a new design methodology in which instead of replicating tiles of core-accelerator pairs, a Hardware Library is shared between cores. This resource provides commonly used routines implemented in hardware logic. Our methodology reduces the total logic needed for these systems by 37%. This allows designers to expose the speed of hardware acceleration with only marginally more logic than if the application were implemented in software alone.

Education

1. The University of Michigan, Ann Arbor MI
   

PhD Candidate in Computer Science and Engineering

1. The University of Michigan, Ann Arbor MI
   

MSE in Computer Science and Engineering 2009

1. -Mentor Graphics CSE Honors Student
   

2. -Richard Orenstein Fellowship
   

1. Brown University, Providence RI
   

ScB in Electrical Engineering with Honors 2007

1. -Thesis: Design of a Shared Hardware Library for Multi-Core Environments in FPGA Fabrics
   

2. -Sigma Xi Honors Research Society