| Latest News: |
| A Fully Integrated Digital PLL-based Transmitter for 802.15.4 Presented at the 2011 IEEE RFIC Symposium in Baltimore, Maryland: |
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Title: A Fully Integrated Digital PLL-based Transmitter for 802.15.4
Authors: Mohammad Mahdi Ghahramani, Mark A. Ferriss, Michael P. Flynn
University of Michigan
Location: Baltimore, Maryland, May 2011
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Abstract: A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers -2dBm of output power. The core PLL is free of in-band fractional spurs. The closest measured spur is below 60dBc at 5MHz offset. The transmitter (including PA), implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm2.
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| 65nm CMOS flexible radio to be presented in September at the IEEE Custom Integrated Circuits Conference in San Jose, California: |
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Abstract: The modern day desire for ubiquitous connectivity using multiple standards and bands necessitates the development of flexible, software-configurable receivers. One of the challenges of creating such receivers is the design of low power, configurable filters for rejecting interferers and adjacent channels. Analog op-amp based filters become difficult to design at the reduced supply voltages of deep submicron processes. Digital filters require significant over-sampling with a higher resolution ADC, at the expense of higher power consumption. This work presents a better alternative of embedding a software-configurable, discrete time (DT) filter within a SAR ADC (“SARfilter ADC”). A flexible wireless receiver prototype was implemented in 65nm CMOS. This 0.4mm2 configurable receiver was verified with the 2450MHz and 915MHz bands of the IEEE 802.15.4 (Zigbee) standard and the IEEE 802.11 (WiFi) standard. The receiver achieves -95dBm sensitivity and +33dB and +40dB adjacent and alternate channel interferer rejection, respectively, with 802.15.4 packets and -83dBm sensitivity and +41dB, +20MHz interferer rejection with 802.11 packets. Power consumption is 1/3 that of state-of-the-art Zigbee receivers.
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| An Integrated 120 Volt AC Mains Voltage Interface in Standard 130 nm CMOS will be presented at the European Solid-State Circuits Conference (ESSCIRC) in Sevilla, Spain: |
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Title: An Integrated 120 Volt AC Mains Voltage Interface in Standard 130 nm CMOS
Authors: Andres Tamez, Jeffery Fredenburg, and Michael P. Flynn
University of Michigan
Location: Sevilla, Spain, September 2010
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Abstract: Transformers are used to step-down 120 V AC to voltage levels that can be tolerated on-chip. Discrete transformers and off-chip rectifier circuits constitute a significant amount of board area. Although high voltages can be handled on-chip with specially engineered device structures (e.g. DMOS), these techniques require additional mask levels in a CMOS process. This work uses a capacitor structure implemented in standard 130 nm CMOS to enable direct interfacing with 120 V AC mains. An on-chip regulator generates a stabilized low-voltage supply. To our knowledge this is the first conventional CMOS integrated circuit that interfaces directly with the 120 V AC line voltage. This work will be presented at the IEEE European Solid-State Circuits Conference in September 2010 by Andres Tamez.
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Chun Chieh Lee will present a novel record-energy efficient 12 bit hybrid SAR-pipeline ADC at the 2010 Symposium on VLSI Circuits in Honolulu, Hawaii: |
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Title: A 12b 50MS/s 3.5mW SAR Assisted 2-Stage Pipeline ADC
Authors: Chun C. Lee and Michael P. Flynn
University of Michigan
Location: Honolulu, Hawaii, June 2010
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Abstract: A prototype ADC, implemented in 65nm CMOS, achieves a peak ENOB of 10.7b, no missing codes at 12b resolution and consumes only 3.5mW at 50MS/s. A record energy efficiency of 52fJ/conversion.step is achieved. The novel, power-efficient, ADC architecture pipelines a SAR-based MDAC SAR ADC. A large first-stage MDAC resolution in a pipeline ADC improves the overall ADC linearity, power consumption, and relaxes noise and matching requirements. However, in a conventional pipeline ADC it is difficult to implement a large resolution first-stage MDAC because it requires a large number of accurate comparators in the flash sub-ADC and an active front-end S/H. The new architecture employs a SAR, instead of the conventional flash architecture, for the sub-ADC. This eliminates all the drawbacks of a high-resolution MDAC. The use of the SAR architecture for the second stage, helps reduce power and achieve high-resolution, thus eliminating the need for more pipeline stages.
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A new SAR ADC technique presented at VLSI Symposium in Kyoto, Japan: |
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Title: A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13m CMOS
Authors: Joshua Kang and Michael P. Flynn
University of Michigan
Location: Kyoto, Japan, June 2009
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Abstract:A two-comparator architecture, incorporating deliberate comparator offset and pre-amplifier power management, reduces comparator meta-stability and comparator power consumption in a 12b 11MS/s SAR ADC. A prototype, fabricated in 0.13μm CMOS achieves an FOM, SNDR, SFDR and error rate of 311fJ/conversion step, 62.4dB and 72.8dB and <1.9×10-12, respectively, at 11MS/s.
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A new technique for flexible modulation in digital fractional-N modulation is demonstrated and will be presented at CICC 2009 in San Jose, California: |
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Title: A Fractional-N PLL modulator with flexible direct digital phase modulation
Authors: Mark Ferriss, David T. Lin, and Michael P. Flynn
University of Michigan
Location: San Jose, California, September 2009
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Abstract: A 2.6GHz fractional-N synthesizer with a flexible digital modulation scheme is presented. The PLL output is modulated by adding a digital signal directly to the output of the phase detector, in contrast to the typical method of changing the divider ratio. A pre-emphasis filter is used to allow switching rates faster than the loop bandwidth. The transmitter supports GMSK, OQPSK, BSK or any constant envelop modulation scheme. Measurements are presented at 300kBit/sec. The 0.7mm2 prototype in 0.13 frac14;m CMOS consumes 20mA from a 1.5V supply. |
Shahrzad Naraghi Presents Paper at 2009 International Solid State Circuits Conference: |
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Title: A pulse-position modulation analog to digital converter in 90nm CMOS technology
Authors: Shahrzad Naraghi, Matthew Courcy, and Michael Flynn
Location: San Francisco, California, February 2009
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Abstract:
Low-power, small-size analog-to-digital converters (ADC) have numerous applications in areas ranging from implantable biomedical devices to power-aware wireless sensing nodes for environmental monitoring and point-of-care diagnostics. Digital circuits and DSP processors are taking advantage of technology scaling in terms of power, speed, and cost. However, as the technology scaling drops the supply voltage and transistor gain is reduced, there is a greater challenge for analog designers.
Nanometer CMOS technology offers better time resolution by reducing the gate delay. Therefore, if we represent the signal as transition in time rather than voltage, we can employ digital circuits to perform analog processing, take advantage of technology scaling, and reduce power consumption and area significantly.
We designed an ADC architecture based on Pulse Position Modulation (PPM) which relies more on time resolution than on amplitude resolution. The input signal is pulse position modulated at the first step and the information is carried in the form of timing intervals. Timing measurement accuracy presents a major challenge and time accuracy is achievable with low power digital circuits in nanometer CMOS technologies. This digital approach is more power efficient compared with pure analog solutions utilized for amplitude measurement of input signals and makes this architecture more attractive with the improvement of digital CMOS technology. Employing a post processing algorithm significantly improves the effective number of bits and compensates for the drawbacks of non-uniform sampling.
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Group to present two papers at Custom Integrated Circuits Conference in September 2008:
A Reconfigurable FIR Filter Embedded in a 9b Successive Approximation ADC, Joshua Kang, David Lin, Li Li and Michael Flynn, University of Michigan, Ann Arbor, MI
A reconfigurable FIR filter is embedded into a 9b SAR ADC by modifying the input tracking switches of the capacitive DAC. The filter-ADC combination can assist or eliminate the anti-aliasing or channel selection filtering stages in a digital radio receiver. Three different filtering modes are implemented and tested.
A 9Gbit/s Serial Transceiver for On-chip Global Signaling over Lossy Transmission Lines, JunYoung Park, Joshua Kang, Sunghyun Park and Michael Flynn, University of Michigan, Ann Arbor, MI, Qualcomm, San Diego, CA, and Campbell, CA
A 9Gbit/s serial link transceiver for on-chip global signaling is presented. A transmitter serializes the parallel 8b 1.125Gbyte/s data over a 5.8mm lossy on-chip transmission line; the receiver de-serializes the data with a digitally tuning interpolator. The prototype transceiver, implemented in 0.13um 8M CMOS, achieves 9Gbit/s with four pre-defined data patterns and a measured BER is less than 10-10. |
Group to present three papers at
VLSI Symposium in June 2008: |
A 64 ChannelProgrammable Closed-loop Deep Brain Stimulator with 8 Channel Neural Amplifier and Logarithmic ADC
Jongwoo Lee, Hyo-Gyuem Rhew, Daryl Kipke and Michael Flynn
A novel signal-chip 271 μW 2.67mm 2 Closed-loop Deep Brain Stimulator (CDBS) was developed for research and treatment of Parkinson’s Disease. In a new approach, 8 front-end low-noise neural amplifiers (LNAs) are multiplexed to a single high dynamic range logarithmic pipeline ADC. An on-chip digital filter separates the low frequency neural field potential signal from the neural spike energy. To alleviate and treat disease symptoms, 64 DAC stimulator channels generate independent, bi-phasic, stimulation current signals. An on-chip controller sets the stimulation pulse amplitude, duration and repetition rate. This system is more than an order-of-magnitude smaller and more power-efficient than state-of-the-art Parkinson’s treatment devices, making it an ideal platform for research and treatment of the disease.
A 5GHz Fully Integrated Super-regenerative Receiver with On-chip Slot Antenna in 0.13µm CMOS
Dan Shi, Nader Behdad, Jia-Yi Chen, and Michael P. Flynn
A single chip receiver incorporates receiver, antenna and digital baseband, enabling true single chip implementation of WIMS systems. A prototype device incorporates a super-regenerative receiver, an on-chip slot antenna and digital received data synchronization. A capacitively-loaded standing-wave resonator improves energy efficiency. An all-digital PLL timing scheme synchronizes the received data clock. The prototype 5GHz receiver, implemented in 0.13μm CMOS, achieves a data rate of up to 1.2Mb/s, dissipates 6.6mW from a 1.5V supply, and occupies a die area of 2.4mm 2.
A 14b 23MS/s 48mW Resetting SD ADC with 87dB SFDR 11.7b ENOB & 0.5mm 2 area
Chun C. Lee and Michael P. Flynn
A 14b 23MS/s ADC that pipelines a 2nd order resetting SD modulator with a 10b cyclic ADC and requires no front-end S/H is presented. The architecture uses a resetting SDmodulator at the front-end for accuracy and a cyclic ADC at the back-end for residual error quantization. This calibration-free ADC achieves no missing codes, 87dB SFDR and 11.7b ENOB. Fabricated in 0.18 mm CMOS with a core area of 0.5mm2, it consumes 48mW from a 2V supply.
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| Flynn named Guggenheim Fellow: |
Guggenheim fellowships awarded to five faculty: By Jared Wadley, News Service
"Five U-M faculty members have been awarded Guggenheim Fellowships, given annually for distinguished achievement in the
past and exceptional promise for future accomplishments.
The faculty are Michael Flynn, associate professor of electrical engineering and computer science; Enrique García
Santo-Tomás, associate professor of Spanish; Arthur Lupia, Hal R. Varian Collegiate Professor of Political Science;
Roberto Merlin, professor of physics and of electrical engineering and computer science; and Piotr Michalowski,
George G. Cameron Professor of Ancient Near Eastern Civilizations.
"I am really thrilled and grateful to be named a Guggenheim Fellow," says Flynn, who is working with students
to create and improve circuits that convert signals between analog and digital representations. These circuits, he explains,
are key parts to every cell phone, computer and camcorder, but also are important in applications as diverse as medical
imaging and seismic sensing. "The Guggenheim Fellowship will allow me to consider the fundamental limitations of these
circuits, and help guide future research," he says."
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| Novel Log Domain Switched Capacitor Pipeline to be presented at VLSI Symposium: |
Fig. 3: Micro photograph of Logarithmic ADC |
Title: A 2.5mW 80dB DR 36dB SNDR 22MS/s Logarithmic Pipeline ADC
Authors: Jongwoo Lee, Sunghyun Park, Joshua Kang, Jae-sun Seo, Jens Anders and Michael Flynn
University of Michigan
Location: June 12-16, 2007 at Rihga Royal Hotel, Kyoto, Japan VLSI Symposium on VLSI Technology and Circuits
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Abstract:
A switched-capacitor logarithmic pipeline ADC scheme that does not require squaring or any other complex analog functions
is described. This approach is ideal where a high dynamic range, but not a high peak SNDR, is required. A signed, 8-bit
1.5 bit-per-stage logarithmic pipeline ADC is implemented in 0.18µm CMOS. The 22MS/s ADC achieves a measured DR of 80dB
and a measured SNDR of 36dB, occupies 0.56mm2, and consumes 2.54mW from a 1.62V supply. The measured dynamic range figure
of merit is 174dB.
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| Two papers authored by group members to be presented at MTT RFIC 2007: |
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Title: A Compact 5GHz Standing-Wave Resonator-based VCO in 0.13µm CMOS
Authors: Dan Shi, Jack East and Michael P. Flynn
University of Michigan
Location: In Honolulu, Hawaii on June 3-8, 2007 MTT RFIC 2007
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Abstract:
A novel on-chip capacitively-loaded, transmission-line-standing-wave resonator is employed in a low phase noise VCO,
to achieve a measured phase noise of -117dBc/Hz at a 1MHz offset. The prototype 5GHz VCO, implemented in 0.13µm CMOS,
dissipates 3mW from a 1.2V supply, and occupies a compact die area of 0.11mm2. |
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Title: A 0.3mm2 Miniaturized X-Band On-Chip Slot Antenna in 0.13mm CMOS
Authors: Nader Behdad, Dan Shi, Wonbin Hong, Kamal Sarabandi and Michael P. Flynn
University of Michigan
Location: In Honolulu, Hawaii on June 3-8, 2007 MTT RFIC 2007
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Abstract:
An on-chip miniaturized slot antenna integrated with a CMOS LNA, on the same chip, is presented in this paper.
The antenna operates in the 9-10GHz frequency band, occupies a die area of only 0.3mm2, and is fabricated in a
standard 0.13µm RF CMOS process. A LNA implemented on the same substrate is directly matched to the antenna. An
efficient shielding technique is used to shield the antenna from the low-resistivity substrate underneath it.
Measurement results of the fabricated prototype indicate that the antenna shows an active gain of -4.4 dBi and
an efficiency of 9% in spite of its close proximity to the lossy silicon substrate.
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| Mark Ferriss presents paper on novel digital dominant Fractional-N PLL Modulator at ISSCC 2007: |
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Title: A 14mW Fractional-N PLL Modulator with Enhanced Digital Phase Detector and Frequency-Switching Scheme
Authors: Mark Ferriss and Michael Flynn
University of Michigan
Location: 5:10pm on Tuesday, Feb. 13, 2007 at ISSCC 2007
Abstract:
A 2.2GHz fractional-N synthesizer with a digital phase detector and a dual switching
scheme is presented. An additional feedback loop incorporating phase oversampling
helps to achieve a measured noise performance of -133dBc (-106dBc) at a 10MHz
(1MHz) offset. The MSK modulation rate is 927.5kb/s. The 0.7mm2 prototype IC,
implemented in a 0.13µm CMOS process, consumes 14mW from a 1.4V supply.
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| Design Winners for EECS 413 Fall 2006 Final Project Presentations Announced: |
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EECS undergrads Jonathan Brown, Francine Shammami, and John DeBusscher share a National Instruments sponsored prize of
$1,000 for best design project in EECS 413 - Monolithic Amplifier Circuits: Intro to Mixed Signal Design. This course
is an introduction to CMOS analog and mixed signal design and includes a major design project. With an enrollment of 40
students this course is popular with both undergrad and graduate students. This course is taught by Michael Flynn.
Thirteen groups presented their design projects in December. The designs fall into 4 categories: Temperature Sensor;
Cherry Hooper Amplifier; Preamplifier; and Ethernet line driver. All designs are implemented in a commercial 0.25μm CMOS
process and include complete layouts. Design was aided by a full suite of industrial-grade CAD tools from Cadence. The
class selected the best project. |
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Brown, Shammami and DeBusscher designed a novel 1µW temperature sensor. The output of the device is an oscillation
frequency that varies linearly with temperature. Key innovations in this work ensure very low power consumption and
independence from power supply voltage. This innovative work could have applications ranging from RFID tagging of food
shipments to monitoring temperature in high performance microprocessors.
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Michael P. Flynn is named Associate Editor for JSSC
Dr. Flynn has been awarded the title of Associate Editor for the Journal of Solid-State Circuits (JSSC).
See http://sscs.org/jssc.htm for more information on the IEEE Journal of Solid State Circuits.
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| Flynn group presents two papers at CICC 2006: |
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Title: A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS
Authors: Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph Bishop and Michael Flynn
Y. Palaskas, A. Ravi, and R. Bishop are at Intel, Hillsboro, OR.
Location: 8:55am on Tuesday, Sept. 12 at CICC 2006
Abstract:
A 5-bit flash ADC incorporates 20µm-by-20µm inductors to improve both comparator pre-amplification bandwidth and
regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying
the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5dB for
a 5MHz input at 4GS/s, and 23.6dB for a 1GHz input at 3.5GS/s. The power consumption (including clock buffer and ladder) is
227mW at 3.5GS/s. The active area is 0.658mm^2.
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Title: A Low Jitter Multi-Phase PLL with Capacitive Coupling
Authors: J.Y. Park and M. Flynn
University of Michigan, Ann Arbor, MI
Location: 10:50am on Wednesday, Sept. 13 at CICC 2006
Abstract:
Capacitive coupling improves both phase noise and phase accuracy in coupled LC oscillators since the coupling
current is in phase with the regeneration current. A prototype 3 GHz PLL with four LC oscillator stages and
capacitive coupling is fabricated in 0.13um CMOS. The long term measured RMS jitter of the buffered clock from
the PLL is 1.61ps and the pk-pk jitter is 13.33ps.
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Group presents two papers at ISSCC 2006
Sunghyun Park presented a paper on a 4GS/s 4-bit ADC implemented in 0.18um digital CMOS. To our knowledge,
this is the fastest non-interleaved ADC in 0.18um CMOS.
Jia-yi Chen presented a fully integrated, self calibrated, super-regenerative receiver implemented in 0.13um CMOS.
The receiver consumes only 5.6nJ/bit, making it one of the most power-efficient narrow band receivers.
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Jorge Pernillo receives Intel Foundation Fellowship
Jorge Pernillo was selected as a 2006-07 Intel Foundation Fellowship winner. This prestigious fellowship
covers both stipend and tuition.
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