Journals

JILP


Accelerating Meta Data Checks for Software Correctness and Security.
Weihaw Chuang, Satish Narayanasamy and Brad Calder
Journal of Instruction-Level Parallelism 9 (2007) 1-26

IEEE Micro
Top Picks


Patching Processor Design Errors.
Smruthi Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder and Josep Torrellas.
IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, Jan-Feb, 2007

IEEE Micro
Top Picks


BugNet: Recording Application Level Execution for Deterministic Replay Debugging.
Satish Narayanasamy, Gilles Pokam, Brad Calder.
IEEE Micro Special Issue: Top Picks from Computer Architecture Conferences, Jan-Feb, 2006

Conferences

MICRO'09


Offline Symbolic Analysis for Multi-Processor Execution Replay
Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang (James) Yang and Cristiano Pereira
International Symposium on Microarchitecture (MICRO). Dec 2009.

ISCA'09


A Case for an Interleaving Constrained Shared-Memory Multi-Processor.
Jie Yu and Satish Narayanasamy.
International Symposium on Computer Architecture (ISCA). June 2009.

PLDI’09


Effective Sampling for Lightweight Data Race Detection.
Dan Marino, Madan Musuvathi and Satish Narayanasamy.
International Conference on Programming Language Design and Implementation (PLDI). June 2009.

PLDI’07


Automatically Classifying Benign and Harmful Data Races Using Replay Analysis.
Satish Narayanasamy, Zhenghao Wang, Jordan Tigani, Andrew Edwards and Brad Calder.
International Conference on Programming Language Design and Implementation (PLDI). June 2007.

DATE’07


Predicting Faults Based on Anomalies in Speculative Execution.
Satish Narayanasamy, Ayse Coskun and Brad Calder
Design, Automation, and Test in Europe, April 2007. (pdf)

HiPEAC’07


Bounds Checking with Taint-Based Analysis.
Weihaw Chuang, Satish Narayanasamy, Brad Calder and Ranjit Jhala
International Conference on High Performance Embedded Architectures & Compilers, Jan 2007. (pdf)

ICCD’06


Patching Processor Design Errors.
Satish Narayanasamy, Bruce Carneal and Brad Calder
IEEE International Conference on Computer Design, Oct 2006. (pdf)

SoMET’06


Software Profiling for Deterministic Replay Debugging of User Code.
Satish Narayanasamy, Cristiano Pereira and Brad Calder
5th International Conference on Software Methodologies, Tools and Techniques. Oct 2006. (pdf)

ASPLOS’06


Recording Shared Memory Dependencies Using Strata.
Satish Narayanasamy, Cristiano Pereira and Brad Calder
12th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct 2006. (pdf)

ASPLOS’06


Unbounded Page-Based Transactional Memory.
Weihaw Chuang, Satish Narayanasamy, Ganesh Venkatesh, Jack Sampson, Michael Van Biesbrouck, Gilles Pokam, Osvaldo Colavin and Brad Calder
12th International Conference on Architectural Support for Programming Languages and Operating Systems, Oct 2006. (pdf)

SIGMETRICS’06


Automatic Logging of Operating System Effects to Guide Application-Level Architecture Simulation.
Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn and Brad Calder
International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS, June 2006. (pdf)

ISCA '05


BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging.
Satish Narayanasamy, Gilles Pokam, Brad Calder.
32nd International Symposium on Computer Architecture. June 2005. (pdf) (Talk)

IPDPS '05


A Dependency Chain Clustered Microarchitecture.
Satish Narayanasamy, Hong Wang, Perry Wang, John Shen, Brad Calder.
19th IEEE International Parallel & Distributed Processing Symposium. Apr 2005. (pdf) (Talk)

HPCA '04


Creating Converged Trace Schedules Using String Matching. 
Satish Narayanasamy, Yuanfang Hu, Suleyman Sair, Brad Calder. 
10th International Symposium on High Performance Computer Architecture.  Feb 2004. (pdf) (Talk)

HPCA '03


Catching Accurate Profiles in Hardware.
Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese. 
9th International Symposium on High Performance Computer Architecture. Feb 2003. (pdf) (Talk)

Others

Patent


System, Method and Apparatus for Dependency Chain Processing.
Satish Narayanasamy et al.
US Patent 20060070047.Published: March 30, 2006.

HiPC  '00


The Gestalt Decentralised Machine - the Model and its Evaluation. 
Manikanan Narayanan, Ram Rangan, Satish Narayanasamy and Ranjani Parthasarathi. 
7th International Conference on High Performance Computing (poster).  Dec 2000.

Bachelor's
Thesis


Decentralized computing.
 
Manikandan Narayanan, Ram Rangan, Satish Narayanasamy.
Thesis Report, March 2001 , College of Engineering, Anna University.