Design, Fabrication, and Characterization of Field Emission Device

S. W. Pang and M. R. Rakhshandehroo

University of Michigan, Ann Arbor, Michigan 48109-2122, USA

An electron cyclotron resonance source is used to generate a Cl2 plasma and dry etch field emitters in Si. Compared to wet etching, dry etching provides more control on the etch profile and therefore sharper emitter tips with higher packing density can be formed. SiO2 is used as the mask and the emitter geometry is controlled using mask erosion technique. By changing the mask profile and the etch conditions, the lateral and vertical etch rates of SiO2 and Si were controlled and emitter tips with different geometry were formed. Arrays of emitter tips with sidewall angle of 80 oC, 11 µm height, and 2.2 µm basewidth were fabricated and packing density of 4x106 tip/cm2 was achieved.

Dry etching and low temperature plasma oxidation were used to sharpen the fabricated emitter tips. Controlling the overetching time without mask and monitoring the optical emission or mass spectrometric signals allowed the emitter tips to be sharpened precisely. The emitter tip radius in a Cl2 plasma at 0.7 mTorr was reduced from 67 to 22 nm after overetching for 2 min. A thin layer of plasma oxide was also grown on the emitter at room temperature and removed in wet etchant subsequently. This process sharpened the tip radius from 67 to 8 nm after growing 250 nm of plasma oxide. Sharper emitter tips are formed by plasma oxidation compared to thermal oxidation. This could be related to the stress at the Si-SiO2 interface which is much higher for plasma oxidation due to lower growth temperature.

A self-aligned process is developed to fabricate gated field emitters. Thick layer of polyimide is used as the insulator between the emitter and the gate. The insulator layer is planarized and the emitter tip apex is exposed using dry etching. Once the emitter tip apex is exposed, the gate metal is deposited. The distance between the gate and the emitter tip apex is determined by a thin sacrificial plasma oxide layer grown on the emitter tip prior to insulator and gate deposition. Gate-tip spacing as low as 80 nm is achieved using this technique. The emission current from 100 tips at the gate voltage of 100 V was increased from 261 to 598 µA when the tip radius was reduced from 67 to 8 nm by plasma oxidation. Low turn-on voltage of 38 V was obtained from emitters with 193 nm gate-tip spacing. Surface passivation of emitter tips in Cl2 and H2 plasma increased the emission current and reduced the turn-on voltage significantly.

Emitter tips were also coated with Mo silicide and HfC. The emission current increased from 230 µA for uncoated emitters to 268 µA for emitters coated with Mo silicide and 389 µA for emitters coated with HfC. The turn-on voltage reduced from 50 to 41 and 25 V while the breakdown voltage increased from 126 to 129 and 143 V when Mo silicide and HfC were used for coating, respectively, which correspond to reductions of 0.95 and 2.23 eV, respectively, in the effective work function of the emitters. Single emitter tips have similar emission characteristics as high-density field emitter arrays, indicating excellent emission uniformity from the arrays.

Figure 1. Scanning electron micrographs of gated Si emitters fabricated by the self-aligned process. The gate-tip spacing is 140 nm, gate diameter is 600 nm, and tip protrusion is 500 nm.

Figure 2. The gate-tip spacing is 560 nm, the gate diameter is 1120 nm, and the tip protrusion is 0 nm.

Figure 3. The arrays of gated emitter tips shown have gate-tip spacing, gate diameter, and tip protrusion of 467, 1500, and 930 nm, respectively.

Figure 4. Emission current from arrays of 100 gated Si field emitter tips with 1000 V anode voltage. The gate-tip spacing was 250 nm and sharpening was done by plasma oxidation.

Figure 5. Effects of surface passivation on the emission characteristics of gated Si field emitters with 377 nm gate-tip spacing is shown.

Figure 6. Effects of emitter coating on the emission characteristics of gated Si field emission devices. Arrays of 100 emitters with gate-tip spacing of 475 nm were tested at 5X10-8 Torr.

References

  1. M. R. Rakhshandehroo and S. W. Pang, "High Current Density Si Field Emission Devices with Plasma Passivation and HfC Coating", IEEE Trans. Electron Devices 46, no. 4, 792-797 (1999).
  2. M. R. Rakhshandehroo and S. W. Pang, "Fabrication of Self-Aligned Silicon Field Emission Devices and Effects of Surface Passivation on Emission Current", J. Vac. Sci. Technol. B 16, 765-769 (1998).
  3. M. R. Rakhshandehroo, J. W. Weigold, W. C. Tian, and S. W. Pang, "Dry Etching of Si Field Emitters and High Aspect Ratio Resonators using an Inductively Coupled Plasma Source", J. Vac. Sci. Technol. B 16, 2849-2854 (1998).
  4. M. R. Rakhshandehroo and S. W. Pang, "Controlling Self-Aligned Gate-Tip Spacing and Gate Diameter for Si Field Emission Devices", J. Vac. Sci. Technol. B 15, 2777-2781 (1997).
  5. M. Rakhshandehroo and S. W. Pang, "Dry Etching of Field Emitter Tips in Si", J. Vac. Sci. Technol. B 14, 612-616 (1996).
  6. M. Rakhshandehroo, F. Sukardi, and S. W. Pang, "Simulation and Fabrication of High Density Si Field Emitters", J. Vac. Sci. Technol. A 14, 1832-1838 (1996).
  7. M. Rakhshandehroo and S. W. Pang, "Sharpening Si Field Emitter Profile by Dry Etching and Low Temperature Plasma Oxidation", J. Vac. Sci. Technol. B 14, 3697-3701 (1996).

Last Updated: November 19, 2007

E-Mail: pang@eecs.umich.edu 

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