Single Electron Transistors and In Plane Gated Quantum Wire Transistors

S. W. Pang, K. K. Ko, and E. W. Berg

University of Michigan, Ann Arbor, Michigan 48109-2122, USA

Single Electron Transistors (SET) have been fabricated by etching pillars in GaAs/Al0.3Ga0.7As material to form the source-drain region and a self aligned process is used to create an airgap separating the gate from the pillar. (Figure 1) The GaAs/ Al0.3Ga0.7As material system was designed with two tunnel barriers, each 6 nm thick, to provide confinement of electrons on a charge island. The structure was designed to observe single electron effects at room temperature. The use of the airgap between the gate and the pillar reduces the capacitance associated with the gate electrode and increases the temperature at which an SET may operate. The self aligned process has only one critical alignment between the pillar and source contact for ease of processing. With the gate voltage used to electrically constrict the dimensions of the charge island, the physical dimensions of the source-drain pillar, and thus the charge island, are not as critical so the lithography constraints are eased and an SET could be formed in an easier and more reliable process. (Figure 2)

Devices were tested and the tunneling resistance, RT, was extracted for comparison to the design values. (Figure 3) Good agreement was found between RT for measured devices and predicted values. A pillar with a 200 nm diameter, designed to have an RT of 2.9 k, had a measured RT of 4.3 k. Processing effects and less than perfect contacts may have contributed to the deviation from the predicted value. The gate isolation was found to be excellent with only ~1 pA of leakage current for VGS>-35 V for devices with 500 nm gate-pillar separation. The gate current increased quickly as VGS was decreased below -35 V before catastrophic breakdown occurred at ~-60 V. For a device with a pillar diameter of 300 nm and gate-pillar separation of 300 nm, VDS was held constant at 0.3 V while the Vg was varied. The drain current decreased from 6.4 to 5.8 µA as Vg decreased from 0 to -28 V. Further decreases in Vg did not affect the pillar conductance. Potential causes for the lack of strong gate-pillar coupling include sidewall surface states induced during processing, potential problems stemming from the material growth with defect, thickness uniformity or doping problems, and device geometry which may cause screening of the gate bias by the source-drain contacts.

Figure 1. Schematic of single electron transistor fabricated in this work showing the critical dimensions of the air gap, d, and the pillar diameter, Wp.

Figure 2. Micrograph of a self-aligned single electron transistor with the source contact on top and the gate surrounding the pillar. The pillar diameter is 100 nm and the gate-pillar spacing is 500 nm.

Figure 3. Current-voltage measurements for the single electron transistor with a pillar diameter of 200 nm and a gate-pillar spacing of 500 nm.

References

  1. W. C. Tian, J. W. Weigold, and S. W. Pang, "Comparison of Cl2 and F-based dry etching for high aspect ratio Si microstructures etched with an inductively coupled plasma source", J. Vac. Sci. Technol. B 18, 1890-1896 (2000).
  2. W. D. Zhou, J. Sabarinathan, B. Kochman, E. W. Berg, O. Qasaimeh, S. W. Pang, and P. Bhattacharya, "Electrically Injected Single-Defect Photonic Bandgap Surface-Emitting Laser at Room Temperature", Electronics Lett. 36, 1541 (2000).
  3. E. W. Berg and S. W. Pang, "Low Pressure Etching of Nanostructures and Via Holes Using an Inductively Coupled Plasma Source", J. Electrochem. Soc. 146, 775-779 (1999).
  4. M. R. Rakhshandehroo and S. W. Pang, "High Current Density Si Field Emission Devices with Plasma Passivation and HfC Coating", IEEE Trans. Electron Devices 46, no. 4, 792-797 (1999).
  5. E. W. Berg and S. W. Pang, "Optical and Electrical Characteristics of InGaAs and GaAs Quantum Wires after Plasma Passivation in an Inductively Coupled Plasma Source", J. Vac. Sci. Technol. B 17, 2745-2749 (1999).
  6. J. W. Weigold, W. H. Juan, and S. W. Pang, "Dry Etching of Deep Si Trenches for Released Resonators in a Cl2 Plasma", J. Electrochem. Soc. 145, 1767-1771 (1998).
  7. M. R. Rakhshandehroo and S. W. Pang, "Fabrication of Self-Aligned Silicon Field Emission Devices and Effects of Surface Passivation on Emission Current", J. Vac. Sci. Technol. B 16, 765-769 (1998).
  8. S. W. Pang, T. Tamamura, M. Nakao, A. Ozawa, and H. Masuda, "Direct Nano-Printing on Al Substrate using SiC Mold", J. Vac. Sci. Technol. B 16, 1145-1149 (1998).
  9. J. W. Weigold and S. W. Pang, "Fabrication of Thick Si Resonators with a Frontside-Release Etch-Diffusion Process", IEEE J. of Microelectromech. Syst. 7, no. 2, 201-206 (1998).
  10. W. H. Juan and S. W. Pang, "High Aspect Ratio Si Vertical Micromirror Arrays for Optical Switching", IEEE J. of Microelectromech. Syst. 7, no. 2, 207-213 (1998).
  11. M. R. Rakhshandehroo, J. W. Weigold, W. C. Tian, and S. W. Pang, "Dry Etching of Si Field Emitters and High Aspect Ratio Resonators using an Inductively Coupled Plasma Source", J. Vac. Sci. Technol. B 16, 2849-2854 (1998).
  12. J. W. Weigold, W. H. Juan, and S. W. Pang, "Boron Diffusion and Etching of High Aspect Ratio Si Trenches for Released Resonators", J. Vac. Sci. Technol. B 15, 267-272 (1997).
  13. F. Ying, W. H. Juan, and S. W. Pang, "Etching of High Aspect Ratio Microcavity Structures in InP", J. Vac. Sci. Technol. B 15, 665-669 (1997).
  14. M. R. Rakhshandehroo and S. W. Pang, "Controlling Self-Aligned Gate-Tip Spacing and Gate Diameter for Si Field Emission Devices", J. Vac. Sci. Technol. B 15, 2777-2781 (1997).
  15. W. H. Juan and S. W. Pang, "High Reflectivity Micromirrors Fabricated by Coating of High Aspect Ratio Si Sidewalls", J. Vac. Sci. Technol. B 15, 2661-2665 (1997).
  16. W. H. Juan and S. W. Pang, "A Novel Etch/Diffusion Process for Fabricating High Aspect Ratio Si Microstructures", IEEE J. of Microelectromech. Syst. 5, no. 1, 18-23 (1996).
  17. M. Rakhshandehroo and S. W. Pang, "Dry Etching of Field Emitter Tips in Si", J. Vac. Sci. Technol. B 14, 612-616 (1996).
  18. W. H. Juan and S. W. Pang, "Control of Si Etch Profile for Microsensor Fabrication", J. Vac. Sci. Technol. A 14, 1189-1193 (1996).
  19. M. Rakhshandehroo, F. Sukardi, and S. W. Pang, "Simulation and Fabrication of High Density Si Field Emitters", J. Vac. Sci. Technol. A 14, 1832-1838 (1996).
  20. K. K. Ko, S. W. Pang, and M. Dahimene, "Relating Electric Field Distribution of an Electron Cyclotron Resonance Cavity to Dry Etching Characteristics ", J. Vac. Sci. Technol. A 14, 2020-2025 (1996).
  21. S. Thomas III and S. W. Pang, "Dry Etching of Horizontal Distributed Bragg Reflector Mirrors for Waveguide Lasers", J. Vac. Sci. Technol. B 14, 4119-4123 (1996).
  22. W. H. Juan and S. W. Pang, "Controlling Sidewall Smoothness for Micromachined Si Mirrors", J. Vac. Sci. Technol. B 14, 4080-4084 (1996).
  23. M. Rakhshandehroo and S. W. Pang, "Sharpening Si Field Emitter Profile by Dry Etching and Low Temperature Plasma Oxidation", J. Vac. Sci. Technol. B 14, 3697-3701 (1996).
  24. K. K. Ko, E. Berg, and S. W. Pang, "Effects of Etch-Induced Damage on the Electrical Characteristics of In-Plane Gated Quantum Wire Transistors", J. Vac. Sci. Technol. B 14, 3663-3667 (1996).
  25. E. S. Snow, W. H. Juan, S. W. Pang, and P. M. Campbell, "Si Nanostructures Fabricated by Anodic Oxidation with an Atomic Force Microscope and Etching with an Electron Cyclotron Resonance Source", Appl. Phys. Lett. 66, 1729-1731 (1995).
  26. W. H. Juan and S. W. Pang, "High Aspect Ratio Si Etching For Microsensor Fabrication", J. Vac. Sci. Technol. A 13, 834-838 (1995).
  27. K. K. Ko and S. W. Pang, "Deep Via Hole Etching of InP", J. Electrochem. Soc. 142, 3945-3949 (1995).
  28. K. K. Ko, K. Kamath, O. Zia, E. Berg, S. W. Pang, and P. Bhattacharya, "Fabrication of Dry Etched Mirrors for In0.2Ga0.8As/GaAs Multiple Quantum Well Waveguides Using an Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 13, 2709-2713 (1995).
  29. K. T. Sung, W. H. Juan, S. W. Pang, and M. Dahimene, "Dependence of Etch Characteristics on Charge Particles as Measured by Langmuir Probe in a Multipolar Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. A 12, 69-74 (1994).
  30. W. H. Juan and S. W. Pang, "High Aspect Ratio Polyimide Etching Using an Oxygen Plasma Generated by Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 12, 422-426 (1994).
  31. K. T. Sung and S. W. Pang, "Mass Spectrometry and Atomic Force Microscopy Studies of Si Etch Characteristics in Cl2 Plasma Generated by Electron Cyclotron Resonance Source", Jpn. J. Appl. Phys. 33, 7112-7116 (1994).
  32. K. T. Sung, W-Q. Li, S. H. Li, S. W. Pang, and P. K. Bhattacharya, "Application of High-Quality SiO2 Grown By Multipolar ECR Source to Si/SiGe MISFET", Electronics Lett. 29, 277-278 (1993).
  33. L. Davis, K. K. Ko, W-Q. Li, H. C. Sun, Y. Lam, T. Brock, S. W. Pang, P. K. Bhattacharya, and M. J. Rooks, "Photoluminescence and Electro-Optic Properties of Small (25-35 nm) Quantum Boxes", Appl. Phys. Lett. 62, 2766-2768 (1993).
  34. K. T. Sung and S. W. Pang, "Etching of Si with Cl2 using an Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. A 11, 1206-1210 (1993).
  35. C. Thirstrup, S. W. Pang, O. Albrektsen, and J. Hanberg, "Effects of Reactive Ion Etching on Optical and Electro-Optical Properties of GaInAs/InP Based Strip-Loaded Waveguides", J. Vac. Sci. Technol. B 11, 1214-1221 (1993).
  36. K. K. Ko and S. W. Pang, "Controllable Layer by Layer Etching of GaAs with an Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 11, 2275-2279 (1993).
  37. K. T. Sung, W. H. Juan, S. W. Pang, and M. W. Horn, "Low Temperature Etching of Silylated Resist in an Oxygen Plasma Generated by an Electron Cyclotron Resonance Source", J. Electrochem. Soc. 140, 3620-3623 (1993).
  38. J. A. Bride, S. Baskaran, N. Taylor, J. W. Halloran, W. H. Juan, S. W. Pang, and M. O'Donnell, "Photolithographic Micromolding of Ceramics Using Plasma Etched Polyimide Patterns", Appl. Phys. Lett. 63, 3379-3381 (1993).
  39. S. W. Pang, K. T. Sung, and K. K. Ko, "Etching of Photoresist Using Oxygen Plasma Generated by a Multipolar Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 10, 1118-1123 (1992).
  40. K. T. Sung and S. W. Pang, "Low Temperature Silicon Oxidation with Oxygen Plasma Generated by an Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 10, 2211-2216 (1992).
  41. K. T. Sung and S. W. Pang, "Selective Etching of Bilayer Photoresist using Multipolar Electron Cyclotron Resonance Source", J. Electrochem. Soc. 139, 3599-3602 (1992).
  42. S. W. Pang and K. K. Ko, "Comparison Between Etching in Cl2 and BCl3 for Compound Semiconductors using Multipolar Electron Cyclotron Resonance Source", J. Vac. Sci. Technol. B 10, 2703-2707 (1992).
  43. S. W. Pang, Y. Liu, and K. T. Sung, "Etching of GaAs and InP Using a Hybrid Microwave and rf System", J. Vac. Sci. Technol. B 9, 3530-3534 (1991).
  44. D. J. Ehrlich, P.A. Maki, S. W. Pang, M. Rothschild, R. R. Kunz, M. W. Horn, and M. A. Hartney, "Excimer Laser Patterning Technologies for Microfabrication", Tr. J. of Physics 14, 1-11 (1990).
  45. S. W. Pang and M. W. Horn, "Amorphous Carbon Films As Planarization Layers Deposited By Plasma Enhanced Chemical Vapor Deposition", IEEE Electron Device Lett. 11, 391-393 (1990).
  46. S. W. Pang and M. W. Horn, "Plasma Deposited Amorphous Carbon Films As Planarization Layers", J. Vac. Sci. Technol. B 8, 1980-1984 (1990).
  47. M. W. Horn, S. W. Pang, and M. Rothschild, "Plasma Deposited Organosilicon Thin Films As Dry Resists For Deep UV Lithography", J. Vac. Sci. Technol. B 8, 1493-1496 (1990).
  48. S. W. Pang, R. R. Kunz, M. Rothschild, R. B. Goodman, M. W. Horn, and D. J. Ehrlich, "Aluminum Oxides As Imaging Materials For 193-nm Excimer Laser Lithography", J. Vac. Sci. Technol. B 7, 1624-1628 (1989).
  49. S. W. Pang, M. W. Geis, W. D. Goodhue, N. N. Efremow, D. J. Ehrlich, and J. N. Randall, "Pattern Transfer by Dry Etching Through Stencil Masks", J. Vac. Sci. Technol. B 6, 249-252 (1988).
  50. S. W. Pang, "Submicrometer Structure Fabricated by Dry Etching and Masked Ion Beam Lithography", J. Electrochem. Soc. 135, 1526-1529 (1988).
  51. D. J. Ehrlich, J. G. Black, M. Rothschild, and S. W. Pang, "Emerging Technology for in situ processing: Patterning Alternatives", J. Vac. Sci. Technol. B 6, 895 (1988).
  52. S. W. Pang, T. M. Lyszczarz, C. L. Chen, J. P. Donnelly, and J. N. Randall, "Masked ion beam lithography for submicrometer-gate-length transistors", J. Vac. Sci. Technol. B 5, 215-218 (1987).
  53. J. Melngailis, D. J. Ehrlich, S. W. Pang, and J. N. Randall, "Cermet as an Inorganic Resist for Ion Lithography", J. Vac. Sci. Technol. B 5, 379 (1987).
  54. M. W. Geis, N. N. Efremow, S. W. Pang, and A. C. Anderson, "Hot Jet Etching of Pb, GaAs, and Si", J. Vac. Sci. Technol. B 5, 363 (1987).
  55. W. D. Goodhue, S. W. Pang, G. D. Johnson, D. K. Astolfi, and D. J. Ehrlich, "Nanometer Scale Columns In GaAs Fabricated by Angled Ion Beam Assisted Etching", Appl. Phys. Lett. 51, 1726-1728 (1987).
  56. S. W. Pang, J. N. Randall, and M. W. Geis, "Sub-100nm-wide, deep trenches defined by reactive-ion etching", J. Vac. Sci. Technol. B 4, 341-344 (1986).

Last Updated: November 19, 2007

E-Mail: pang@eecs.umich.edu 

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