#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
#install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
#OS: Windows XP 5.1
#Hostname: QUIKQUAK

#Implementation: synthesis

#Sun Aug 29 13:38:00 2010

$ Start of Compile
#Sun Aug 29 13:38:00 2010

Synopsys VHDL Compiler, version comp475rc, Build 060R, built Jan 15 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@N:CD720 : std.vhd(123) | Setting time resolution to ns
Top entity isn't set yet!
@W:CD645 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(5) | Ignoring undefined library smartfusion
@W:CD643 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(6) | Ignoring use clause - smartfusion not found ...
@W:CD645 : lab2fpga.vhd(5) | Ignoring undefined library smartfusion
@W:CD643 : lab2fpga.vhd(6) | Ignoring use clause - smartfusion not found ...
@W:CD645 : lab2fpga_top.vhd(5) | Ignoring undefined library smartfusion
@W:CD643 : lab2fpga_top.vhd(6) | Ignoring use clause - smartfusion not found ...
VHDL syntax check successful!
File Z:\eecs373-f10\labs\lab2\files\lab2fpga\component\Actel\SmartFusionMSS\MSS\2.1.108\mss_comps.vhd changed - recompiling
File Z:\eecs373-f10\labs\lab2\files\lab2fpga\component\work\lab2fpga\MSS_CCC_0\lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd changed - recompiling
File Z:\eecs373-f10\labs\lab2\files\lab2fpga\component\work\lab2fpga\lab2fpga.vhd changed - recompiling
File Z:\eecs373-f10\labs\lab2\files\lab2fpga\component\work\lab2fpga_top\lab2fpga_top.vhd changed - recompiling
Warning:Can't open record reference file@N: CD630 :"C:\Actel\projects\lab2fpga\lab2fpga\component\work\lab2fpga_top\lab2fpga_top.vhd":8:7:8:18|Synthesizing work.lab2fpga_top.def_arch 
@W:CD280 : lab2fpga_top.vhd(27) | Unbound component VCC mapped to black box
@W:CD280 : lab2fpga_top.vhd(47) | Unbound component GND mapped to black box
@N:CD630 : lab2fpga_top.vhd(47) | Synthesizing work.gnd.syn_black_box 
Post processing for work.gnd.syn_black_box
@N:CD630 : lab2fpga.vhd(8) | Synthesizing work.lab2fpga.def_arch 
@N:CD630 : mss_comps.vhd(168) | Synthesizing work.mssint.def_arch 
Post processing for work.mssint.def_arch
@N:CD630 : mss_comps.vhd(4) | Synthesizing work.inbuf_mss.def_arch 
Post processing for work.inbuf_mss.def_arch
@N:CD630 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(8) | Synthesizing work.lab2fpga_tmp_mss_ccc_0_mss_ccc.def_arch 
@W:CD280 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(88) | Unbound component RCOSC mapped to black box
@N:CD630 : lab2fpga_top.vhd(27) | Synthesizing work.vcc.syn_black_box 
Post processing for work.vcc.syn_black_box
@N:CD630 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(88) | Synthesizing work.rcosc.syn_black_box 
Post processing for work.rcosc.syn_black_box
@N:CD630 : mss_comps.vhd(947) | Synthesizing work.mss_ccc.def_arch 
Post processing for work.mss_ccc.def_arch
Post processing for work.lab2fpga_tmp_mss_ccc_0_mss_ccc.def_arch
@W:CL240 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(38) | LPXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(37) | MAINXIN_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(36) | RCOSC_CLKOUT is not assigned a value (floating) - a simulation mismatch is possible 
@N:CD630 : mss_comps.vhd(422) | Synthesizing work.mss_apb.def_arch 
Post processing for work.mss_apb.def_arch
Post processing for work.lab2fpga.def_arch
Post processing for work.lab2fpga_top.def_arch
@W:CL168 : lab2fpga_top.vhd(68) | Pruning instance 	GND - not in use ... 
@W:CL168 : lab2fpga_top.vhd(57) | Pruning instance 	VCC - not in use ... 
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(10) | Input CLKA is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(11) | Input CLKA_PAD is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(12) | Input CLKA_PADP is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(13) | Input CLKA_PADN is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(14) | Input CLKB is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(15) | Input CLKB_PAD is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(16) | Input CLKB_PADP is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(17) | Input CLKB_PADN is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(18) | Input CLKC is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(19) | Input CLKC_PAD is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(20) | Input CLKC_PADP is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(21) | Input CLKC_PADN is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(22) | Input MAINXIN is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(23) | Input LPXIN is unused
@W:CL159 : lab2fpga_tmp_MSS_CCC_0_MSS_CCC.vhd(24) | Input MAC_CLK is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Aug 29 13:38:01 2010

###########################################################]
Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2009.12A
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  

Automatic dissolve at startup in view:work.lab2fpga(def_arch) of MSS_CCC_0(lab2fpga_tmp_MSS_CCC_0_MSS_CCC)
Automatic dissolve at startup in view:work.lab2fpga_top(def_arch) of lab2fpga_0(lab2fpga)

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Writing Analyst data base C:\Actel\projects\lab2fpga\lab2fpga\synthesis\lab2fpga_top.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 55MB peak: 57MB)

Writing EDIF Netlist and constraint files
D-2009.12A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 56MB peak: 57MB)

@W:MT246 : lab2fpga.vhd(640) | Blackbox MSSINT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W:MT246 : lab2fpga.vhd(360) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Aug 29 13:38:07 2010
#


Top view:               lab2fpga_top
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: 4.491

                   Requested     Estimated     Requested     Estimated               Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group           
----------------------------------------------------------------------------------------------------------------
System             100.0 MHz     181.5 MHz     10.000        5.509         4.491     system     default_clkgroup
================================================================================================================





Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                 Starting                                                        Arrival          
Instance                         Reference     Type        Pin         Net                       Time        Slack
                                 Clock                                                                            
------------------------------------------------------------------------------------------------------------------
lab2fpga_0.MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT      N_CLKA_RCOSC              0.000       4.491
lab2fpga_0.MSSINT_GPI_0          System        MSSINT      Y           MSSINT_GPI_0_Y            0.000       9.678
lab2fpga_0.MSSINT_GPI_1          System        MSSINT      Y           MSSINT_GPI_1_Y            0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     EMCCLK      MSS_ADLIB_INST_EMCCLK     0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[24]     MSSINT_GPO_24_A           0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[25]     MSSINT_GPO_25_A           0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[26]     MSSINT_GPO_26_A           0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[27]     MSSINT_GPO_27_A           0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[28]     MSSINT_GPO_28_A           0.000       9.678
lab2fpga_0.MSS_ADLIB_INST        System        MSS_APB     GPO[29]     MSSINT_GPO_29_A           0.000       9.678
==================================================================================================================


Ending Points with Worst Slack
******************************

                              Starting                                                          Required          
Instance                      Reference     Type        Pin           Net                       Time         Slack
                              Clock                                                                               
------------------------------------------------------------------------------------------------------------------
lab2fpga_0.MSS_ADLIB_INST     System        MSS_APB     FCLK          MSS_ADLIB_INST_FCLK       10.000       4.491
lab2fpga_0.MSSINT_GPO_24      System        MSSINT      A             MSSINT_GPO_24_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_25      System        MSSINT      A             MSSINT_GPO_25_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_26      System        MSSINT      A             MSSINT_GPO_26_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_27      System        MSSINT      A             MSSINT_GPO_27_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_28      System        MSSINT      A             MSSINT_GPO_28_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_29      System        MSSINT      A             MSSINT_GPO_29_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_30      System        MSSINT      A             MSSINT_GPO_30_A           10.000       9.678
lab2fpga_0.MSSINT_GPO_31      System        MSSINT      A             MSSINT_GPO_31_A           10.000       9.678
lab2fpga_0.MSS_ADLIB_INST     System        MSS_APB     EMCCLKRTN     MSS_ADLIB_INST_EMCCLK     10.000       9.678
==================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      5.509
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     4.491

    Number of logic level(s):                1
    Starting point:                          lab2fpga_0.MSS_CCC_0.I_RCOSC / CLKOUT
    Ending point:                            lab2fpga_0.MSS_ADLIB_INST / FCLK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                                Pin        Pin               Arrival     No. of    
Name                              Type        Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------
lab2fpga_0.MSS_CCC_0.I_RCOSC      RCOSC       CLKOUT     Out     0.000     0.000       -         
N_CLKA_RCOSC                      Net         -          -       0.322     -           1         
lab2fpga_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     CLKA       In      -         0.322       -         
lab2fpga_0.MSS_CCC_0.I_MSSCCC     MSS_CCC     GLAMSS     Out     4.866     5.188       -         
MSS_ADLIB_INST_FCLK               Net         -          -       0.322     -           1         
lab2fpga_0.MSS_ADLIB_INST         MSS_APB     FCLK       In      -         5.509       -         
=================================================================================================
Total path delay (propagation time + setup) of 5.509 is 4.866(88.3%) logic and 0.643(11.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA256_Std
Report for cell lab2fpga_top.def_arch
  Core Cell usage:
              cell count     area count*area
               GND     3      0.0        0.0
            MSSINT    10      0.0        0.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     3      0.0        0.0


                   -----          ----------
             TOTAL    19                 0.0


  IO Cell usage:
              cell count
             INBUF     2
         INBUF_MSS     1
            OUTBUF     8
                   -----
             TOTAL    11


Core Cells         : 0 of 4608 (0%)
IO Cells           : 11 of 66 (17%)

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Sun Aug 29 13:38:07 2010

###########################################################]