#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010 #install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A #OS: 6.1 #Hostname: WIN-K2PJVCLULR9 #Implementation: synthesis #Fri Aug 27 21:57:18 2010 $ Start of Compile #Fri Aug 27 21:57:18 2010 Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010 Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved @I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v" @I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\hdl\enc3to8.v" @I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\hdl\enc3to8wraper.v" @I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v" @I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\DirectCore\CoreAPB3\3.0.103\rtl\vlog\core_obfuscated\coreapb3.v" @I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_top\lab4_top.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module lab4_top @W:CG775 : coreapb3.v(13) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(13) | Synthesizing module CAPB3O @N:CG364 : coreapb3.v(13) | Synthesizing module CoreAPB3 APB_DWIDTH=6'b100000 RANGESIZE=21'b000000000000100000000 IADDR_ENABLE=1'b0 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 CAPB3O1I=32'b00000000000000000000000000001000 CAPB3I1I=32'b00000000000000000000000000001000 CAPB3l1I=8'b00001100 CAPB3OOl=8'b00001000 CAPB3IOl=8'b00000100 CAPB3lOl=8'b00000000 CAPB3OIl=8'b00000100 CAPB3IIl=8'b00000000 CAPB3lIl=8'b00000000 CAPB3Oll=16'b0000000000000001 CAPB3Ill=16'b0000000000000000 CAPB3lll=16'b0000000000000000 CAPB3O0l=16'b0000000000000000 CAPB3I0l=16'b0000000000000000 CAPB3l0l=16'b0000000000000000 CAPB3O1l=16'b0000000000000000 CAPB3I1l=16'b0000000000000000 CAPB3l1l=16'b0000000000000000 CAPB3OO0=16'b0000000000000000 CAPB3IO0=16'b0000000000000000 CAPB3lO0=16'b0000000000000000 CAPB3OI0=16'b0000000000000000 CAPB3II0=16'b0000000000000000 CAPB3lI0=16'b0000000000000000 CAPB3Ol0=16'b0000000000000000 Generated name = CoreAPB3_Z1 @N:CG364 : smartfusion.v(1814) | Synthesizing module VCC @E:CG389 : lab4_top.v(476) | Reference to undefined module lab4_mss @E:CG389 : lab4_top.v(476) | Illegal or Unsupported Syntax within black box. Use: // synthesis translate_off { unsupported Verilog } // synthesis translate_on @E:CG389 : lab4_top.v(476) | Alternatively, set the builtin compiler directive IGNORE_VERILOG_BLACKBOX_GUTS in the Verilog tab of the UI or set `define IGNORE_VERILOG_BLACKBOX_GUTS in any Verilog file. @N:CG364 : smartfusion.v(1133) | Synthesizing module GND @N:CG364 : enc3to8.v(3) | Synthesizing module enc3to8 @N:CG364 : enc3to8wraper.v(3) | Synthesizing module reg_apb_wrp @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 2 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 3 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 4 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 5 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 6 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 7 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 8 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 9 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 10 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 11 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 12 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 13 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 14 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 15 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 16 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 17 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 18 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 19 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 20 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 21 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 22 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 23 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 24 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 25 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 26 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 27 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 28 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 29 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 30 of sw_reg @W:CG134 : enc3to8wraper.v(30) | No assignment to bit 31 of sw_reg @W:CL170 : enc3to8wraper.v(41) | Pruning bit <31> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <30> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <29> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <28> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <27> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <26> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <25> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <24> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <23> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <22> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <21> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <20> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <19> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <18> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <17> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <16> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <15> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <14> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <13> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <12> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <11> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <10> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <9> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <8> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <7> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <6> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <5> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <4> of led_reg[31:0] - not in use ... @W:CL170 : enc3to8wraper.v(41) | Pruning bit <3> of led_reg[31:0] - not in use ... @A: : enc3to8wraper.v(41) | Feedback mux created for signal PRDATA[31:0]. Did you forget the set/reset assignment for this signal? Specifying a reset value will improve timing and area @N:CG364 : lab4_top.v(5) | Synthesizing module lab4_top @W:CG141 : lab4_top.v(476) | Creating black_box for lab4_mss Making port MSS_RESET_N a bidir Making port MSSPSEL a bidir Making port MSSPENABLE a bidir Making port MSSPWRITE a bidir Making port MSSPREADY a bidir Making port MSSPSLVERR a bidir Making port M2F_RESET_N a bidir Making port FAB_CLK a bidir Making port MSSPADDR an input Making port MSSPRDATA an input Making port MSSPWDATA an input @W:CG360 : lab4_top.v(106) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[0] @W:CG360 : lab4_top.v(107) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[1] @W:CG360 : lab4_top.v(108) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[2] @W:CG360 : lab4_top.v(109) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[3] @W:CG360 : lab4_top.v(110) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[4] @W:CG360 : lab4_top.v(111) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[5] @W:CG360 : lab4_top.v(112) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[6] @W:CG360 : lab4_top.v(113) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[7] @W:CG360 : lab4_top.v(114) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[8] @W:CG360 : lab4_top.v(115) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[9] @W:CG360 : lab4_top.v(116) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[10] @W:CG360 : lab4_top.v(117) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[11] @W:CG360 : lab4_top.v(118) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[12] @W:CG360 : lab4_top.v(119) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[13] @W:CG360 : lab4_top.v(120) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[14] @W:CG360 : lab4_top.v(121) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[15] @W:CG360 : lab4_top.v(122) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[16] @W:CG360 : lab4_top.v(123) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[17] @W:CG360 : lab4_top.v(124) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[18] @W:CG360 : lab4_top.v(125) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PADDR_[19] @W:CG360 : lab4_top.v(162) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[0] @W:CG360 : lab4_top.v(163) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[1] @W:CG360 : lab4_top.v(164) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[2] @W:CG360 : lab4_top.v(165) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[3] @W:CG360 : lab4_top.v(166) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[4] @W:CG360 : lab4_top.v(167) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[5] @W:CG360 : lab4_top.v(168) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[6] @W:CG360 : lab4_top.v(169) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[7] @W:CG360 : lab4_top.v(170) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[8] @W:CG360 : lab4_top.v(171) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[9] @W:CG360 : lab4_top.v(172) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[10] @W:CG360 : lab4_top.v(173) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[11] @W:CG360 : lab4_top.v(174) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[12] @W:CG360 : lab4_top.v(175) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[13] @W:CG360 : lab4_top.v(176) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[14] @W:CG360 : lab4_top.v(177) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[15] @W:CG360 : lab4_top.v(178) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[16] @W:CG360 : lab4_top.v(179) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[17] @W:CG360 : lab4_top.v(180) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[18] @W:CG360 : lab4_top.v(181) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[19] @W:CG360 : lab4_top.v(182) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[20] @W:CG360 : lab4_top.v(183) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[21] @W:CG360 : lab4_top.v(184) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[22] @W:CG360 : lab4_top.v(185) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[23] @W:CG360 : lab4_top.v(186) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[24] @W:CG360 : lab4_top.v(187) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[25] @W:CG360 : lab4_top.v(188) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[26] @W:CG360 : lab4_top.v(189) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[27] @W:CG360 : lab4_top.v(190) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[28] @W:CG360 : lab4_top.v(191) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[29] @W:CG360 : lab4_top.v(192) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[30] @W:CG360 : lab4_top.v(193) | No assignment to wire lab4_mss_0_MSS_MASTER_APB_PWDATA_[31] @W:CL156 : lab4_top.v(201) | *Input un1_lab4_mss_0_MSS_MASTER_APB_PADDR_[0][23:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible @W:CL156 : lab4_top.v(201) | *Input un1_lab4_mss_0_MSS_MASTER_APB_PWDATA_[0][31:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible @W:CL156 : lab4_top.v(476) | *Input un1_lab4_mss_0_MSS_MASTER_APB_PADDR_[0][19:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible @W:CL156 : lab4_top.v(476) | *Input un1_lab4_mss_0_MSS_MASTER_APB_PWDATA_[0][31:0] to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible @W:CL246 : enc3to8wraper.v(19) | Input port bits 31 to 3 of PWDATA[31:0] are unused @W:CL246 : coreapb3.v(217) | Input port bits 23 to 12 of PADDR[23:0] are unused @W:CL159 : coreapb3.v(208) | Input PRESETN is unused @W:CL159 : coreapb3.v(210) | Input PCLK is unused @W:CL159 : coreapb3.v(356) | Input PRDATAS1 is unused @W:CL159 : coreapb3.v(363) | Input PRDATAS2 is unused @W:CL159 : coreapb3.v(370) | Input PRDATAS3 is unused @W:CL159 : coreapb3.v(377) | Input PRDATAS4 is unused @W:CL159 : coreapb3.v(384) | Input PRDATAS5 is unused @W:CL159 : coreapb3.v(391) | Input PRDATAS6 is unused @W:CL159 : coreapb3.v(398) | Input PRDATAS7 is unused @W:CL159 : coreapb3.v(405) | Input PRDATAS8 is unused @W:CL159 : coreapb3.v(412) | Input PRDATAS9 is unused @W:CL159 : coreapb3.v(419) | Input PRDATAS10 is unused @W:CL159 : coreapb3.v(426) | Input PRDATAS11 is unused @W:CL159 : coreapb3.v(433) | Input PRDATAS12 is unused @W:CL159 : coreapb3.v(440) | Input PRDATAS13 is unused @W:CL159 : coreapb3.v(447) | Input PRDATAS14 is unused @W:CL159 : coreapb3.v(454) | Input PRDATAS15 is unused @W:CL159 : coreapb3.v(458) | Input PREADYS1 is unused @W:CL159 : coreapb3.v(460) | Input PREADYS2 is unused @W:CL159 : coreapb3.v(462) | Input PREADYS3 is unused @W:CL159 : coreapb3.v(464) | Input PREADYS4 is unused @W:CL159 : coreapb3.v(466) | Input PREADYS5 is unused @W:CL159 : coreapb3.v(468) | Input PREADYS6 is unused @W:CL159 : coreapb3.v(470) | Input PREADYS7 is unused @W:CL159 : coreapb3.v(472) | Input PREADYS8 is unused @W:CL159 : coreapb3.v(474) | Input PREADYS9 is unused @W:CL159 : coreapb3.v(476) | Input PREADYS10 is unused @W:CL159 : coreapb3.v(478) | Input PREADYS11 is unused @W:CL159 : coreapb3.v(480) | Input PREADYS12 is unused @W:CL159 : coreapb3.v(482) | Input PREADYS13 is unused @W:CL159 : coreapb3.v(484) | Input PREADYS14 is unused @W:CL159 : coreapb3.v(486) | Input PREADYS15 is unused @W:CL159 : coreapb3.v(490) | Input PSLVERRS1 is unused @W:CL159 : coreapb3.v(492) | Input PSLVERRS2 is unused @W:CL159 : coreapb3.v(494) | Input PSLVERRS3 is unused @W:CL159 : coreapb3.v(496) | Input PSLVERRS4 is unused @W:CL159 : coreapb3.v(498) | Input PSLVERRS5 is unused @W:CL159 : coreapb3.v(500) | Input PSLVERRS6 is unused @W:CL159 : coreapb3.v(502) | Input PSLVERRS7 is unused @W:CL159 : coreapb3.v(504) | Input PSLVERRS8 is unused @W:CL159 : coreapb3.v(506) | Input PSLVERRS9 is unused @W:CL159 : coreapb3.v(508) | Input PSLVERRS10 is unused @W:CL159 : coreapb3.v(510) | Input PSLVERRS11 is unused @W:CL159 : coreapb3.v(512) | Input PSLVERRS12 is unused @W:CL159 : coreapb3.v(514) | Input PSLVERRS13 is unused @W:CL159 : coreapb3.v(516) | Input PSLVERRS14 is unused @W:CL159 : coreapb3.v(518) | Input PSLVERRS15 is unused @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Aug 27 21:57:21 2010 ###########################################################]