#Build: Synplify Pro D-2009.12A, Build 040R, Jan 20 2010
#install: C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A
#OS:  6.1
#Hostname: WIN-K2PJVCLULR9

#Implementation: synthesis

#Thu Aug 26 11:32:42 2010

$ Start of Compile
#Thu Aug 26 11:32:42 2010

Synopsys Verilog Compiler, version comp475rc, Build 060R, built Jan 15 2010
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved

@I::"C:\Actel\Libero_v9.0\Synopsys\synplify_D200912A\lib\proasic\smartfusion.v"
@I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\Actel\SmartFusionMSS\MSS\2.2.101\mss_comps.v"
@I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_mss\MSS_CCC_0\lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v"
@I::"Z:\eecs373-f10\labs\lab4\files\lab4fpga\component\work\lab4_mss\lab4_mss.v"
Verilog syntax check successful!
Selecting top level module lab4_mss
@N:CG364 : mss_comps.v(23) | Synthesizing module INBUF_MSS

@N:CG364 : smartfusion.v(1814) | Synthesizing module VCC

@N:CG364 : mss_comps.v(151) | Synthesizing module MSS_CCC

@N:CG364 : smartfusion.v(2566) | Synthesizing module RCOSC

@N:CG364 : smartfusion.v(1133) | Synthesizing module GND

@N:CG364 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(5) | Synthesizing module lab4_mss_tmp_MSS_CCC_0_MSS_CCC

@N:CG364 : mss_comps.v(680) | Synthesizing module MSS_APB

@N:CG364 : lab4_mss.v(5) | Synthesizing module lab4_mss

@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(62) | *Output RCOSC_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(63) | *Output MAINXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL157 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(64) | *Output LPXIN_CLKOUT has undriven bits - a simulation mismatch is possible 
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(36) | Input CLKA is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(37) | Input CLKA_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(38) | Input CLKA_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(39) | Input CLKA_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(40) | Input CLKB is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(41) | Input CLKB_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(42) | Input CLKB_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(43) | Input CLKB_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(44) | Input CLKC is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(45) | Input CLKC_PAD is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(46) | Input CLKC_PADP is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(47) | Input CLKC_PADN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(48) | Input MAINXIN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(49) | Input LPXIN is unused
@W:CL159 : lab4_mss_tmp_MSS_CCC_0_MSS_CCC.v(50) | Input MAC_CLK is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Aug 26 11:32:44 2010

###########################################################]
Synopsys Actel Technology Mapper, Version map500act, Build 058R, Built Jan 18 2010 09:16:23
Copyright (C) 1994-2010, Synopsys Inc.  All Rights Reserved
Product Version D-2009.12A
@N:MF249 :  | Running in 32-bit mode. 
@N:MF258 :  | Gated clock conversion disabled  

@W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(62) | tristate driver RCOSC_CLKOUT on net RCOSC_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(63) | tristate driver MAINXIN_CLKOUT on net MAINXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) 
@W:MO111 : lab4_mss_tmp_mss_ccc_0_mss_ccc.v(64) | tristate driver LPXIN_CLKOUT on net LPXIN_CLKOUT has its enable tied to GND (module lab4_mss_tmp_MSS_CCC_0_MSS_CCC) 
Automatic dissolve at startup in view:work.lab4_mss(verilog) of MSS_CCC_0(lab4_mss_tmp_MSS_CCC_0_MSS_CCC)

Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished preparing to map (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished technology mapping (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Writing Analyst data base Z:\eecs373-f10\labs\lab4\files\lab4fpga\synthesis\lab4_mss.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 55MB peak: 57MB)

Writing EDIF Netlist and constraint files
D-2009.12A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 56MB peak: 57MB)

@W:MT246 : lab4_mss.v(50) | Blackbox MSS_APB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Aug 26 11:33:01 2010
#


Top view:               lab4_mss
Library name:           smartfusion
Operating conditions:   COMWCSTD ( T = 70.0, V = 1.42, P = 1.74, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        smartfusion
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.. 



Performance Summary 
*******************


Worst slack in design: 4.426

                   Requested     Estimated     Requested     Estimated               Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type       Group           
----------------------------------------------------------------------------------------------------------------
System             100.0 MHz     179.4 MHz     10.000        5.574         4.426     system     default_clkgroup
================================================================================================================





Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                      Starting                                                       Arrival          
Instance              Reference     Type        Pin        Net                       Time        Slack
                      Clock                                                                           
------------------------------------------------------------------------------------------------------
MSS_CCC_0.I_RCOSC     System        RCOSC       CLKOUT     N_CLKA_RCOSC              0.000       4.426
MSS_ADLIB_INST        System        MSS_APB     EMCCLK     MSS_ADLIB_INST_EMCCLK     0.000       9.678
======================================================================================================


Ending Points with Worst Slack
******************************

                   Starting                                                            Required          
Instance           Reference     Type        Pin             Net                       Time         Slack
                   Clock                                                                                 
---------------------------------------------------------------------------------------------------------
MSS_ADLIB_INST     System        MSS_APB     SYNCCLKFDBK     FAB_CLK_c                 10.000       4.426
MSS_ADLIB_INST     System        MSS_APB     FCLK            MSS_ADLIB_INST_FCLK       10.000       4.491
MSS_ADLIB_INST     System        MSS_APB     EMCCLKRTN       MSS_ADLIB_INST_EMCCLK     10.000       9.678
=========================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    + Estimated clock delay at ending point: 0.000
    = Required time:                         10.000

    - Propagation time:                      5.574
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (critical) :                     4.426

    Number of logic level(s):                1
    Starting point:                          MSS_CCC_0.I_RCOSC / CLKOUT
    Ending point:                            MSS_ADLIB_INST / SYNCCLKFDBK
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                     Pin             Pin               Arrival     No. of    
Name                   Type        Name            Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
MSS_CCC_0.I_RCOSC      RCOSC       CLKOUT          Out     0.000     0.000       -         
N_CLKA_RCOSC           Net         -               -       0.322     -           1         
MSS_CCC_0.I_MSSCCC     MSS_CCC     CLKA            In      -         0.322       -         
MSS_CCC_0.I_MSSCCC     MSS_CCC     GLB             Out     4.866     5.188       -         
FAB_CLK_c              Net         -               -       0.386     -           2         
MSS_ADLIB_INST         MSS_APB     SYNCCLKFDBK     In      -         5.574       -         
===========================================================================================
Total path delay (propagation time + setup) of 5.574 is 4.866(87.3%) logic and 0.707(12.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Target Part: A2F200M3F_FBGA256_Std
Report for cell lab4_mss.verilog
  Core Cell usage:
              cell count     area count*area
               GND     2      0.0        0.0
           MSS_APB     1      0.0        0.0
           MSS_CCC     1      0.0        0.0
             RCOSC     1      0.0        0.0
               VCC     2      0.0        0.0


                   -----          ----------
             TOTAL     7                 0.0


  IO Cell usage:
              cell count
             INBUF    34
         INBUF_MSS     1
            OUTBUF    57
                   -----
             TOTAL    92


Core Cells         : 0 of 4608 (0%)
IO Cells           : 92 of 66 (139%)

  RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)

Mapper successful!
Process took 0h:00m:05s realtime, 0h:00m:02s cputime
# Thu Aug 26 11:33:01 2010

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