THIS IS THE FALL 2014 VERSION OF CLASS

LINK TO THE CURRENT CLASS

EECS 373: Design of Microprocessor-Based Systems (F'14)



Announcements


Course Administrivia

Course:
  EECS 373, Fall 2014, 4 Units, CN: 10471
Instructional Staff:
  Prabal Dutta (Instructor)
  Matt Smith (Lab Instructor)
  Chris Fulara (IA)
  Chris Heyer (IA)
  Ryan Wooster (IA)
  Dili Hu (Grader)
Homepage:
  http://www.eecs.umich.edu/~prabal/teaching/eecs373
Lecture:
  2150 DOW
  Tue/Thu: 10:30 AM - 12:00 PM
Lab:
  2334 EECS
  Tue: 3:00 PM - 6:00 PM (CN: 10473)
  Wed: 3:00 PM - 6:00 PM (CN: 10474)
  Thu: 6:00 PM - 9:00 PM (CN: 10475)
Office Hours:
  Tue: 1:30 PM - 3:00 PM (4773 BBB)

Course Description

This class is focused on the principles and practices of modern embedded systems design. In class, we will focus on computer architecture beyond the CPU, fundamentals of the hardware/software interface, techniques for sensing and controlling the physical world, and a few other topics. In lab, we will focus on the ARM Cortex-M3, Actel FPGAs, and other supporting hardware, to learn how to design, build, and program embedded systems. Labs during the first half of the course will focus on essential topics. The second half of the course will focus on the design and implementation of non-trivial, open-ended project involving both hardware and software. The labs and project will require a substantial amount of time -- this is a lab-intensive class with a heavy workload.

Syllabus (Tentative)

Day Date Topic Lead(s) Lab
ARM System Architecture
1 Sep 2 Introduction (PPT | PDF | 6up) Dutta Lab # 1 : Hardware Tools
2 Sep 4 Architecture, Assembly, ABI (PPT | PDF | 6up) Dutta
3 Sep 9 Assembly, ABI, Toolchains (PPT | PDF | 6up) Ghena Lab # 2 : Software Tools
4 Sep 11 MMIO and APB (PPT | PDF | 6up) Ghena
5 Sep 16 Memory/Peripheral Bus: AMBA (PPT | PDF | 6up) Dutta Lab # 3 : Memory-Mapped I/O
6 Sep 18 Memory Bus, Interrupts (1) (PPT | PDF | 6up) Dutta
7 Sep 23 Interrupts, ARM NVIC (PPT | PDF | 6up) Dutta Lab # 4 : Interrupts
8 Sep 25 Timers (PPT | PDF | 6up) Dutta
Peripheral Interfacing
9 Sep 30 Timers (continued) and Digital I/O (PPT | PDF | 6up) Dutta Lab # 5 : Clocks, Counters, and Timers
10 Oct 2 Serial buses: UART, SPI, and I2C (PPT | PDF | 6up) Dutta
11 Oct 7 Sampling, ADCs, DACs (PPT | PDF | 6up) Dutta Lab # 6 : Serial Bus Interfacing
12 Oct 9 Catch up and Review Dutta
13 Oct 14 NO LECTURE: Fall Study Break   Lab # 6 : Serial Bus Interfacing
14 Oct 16 Midterm  
15 Oct 21 Research Projects Overview (PPT | PDF | 6up) Dutta Lab # 7 : ADC/DAC Data Converters
16 Oct 23 Project Overview (PPT | PDF | 6up) Pannuto
Projects
17 Oct 28 Project Discussions and Breakout Meetings All Projects
18 Oct 30 PCB Design (PDF | 6up) DeBruin
19 Nov 4 NO LECTURE: Project Meetings Students
& Staff
Projects
20 Nov 6
21 Nov 11 NO LECTURE: Special Topics Meetings Students
& Staff
Projects
22 Nov 13
23 Nov 18 TBD TBD Projects
24 Nov 20 Special Topics: Sensing
- Temperature/Humidity Sensors
- Accelerometers
- Microphones
- NFC
Students Projects
25 Nov 25 Special Topics: Computation and Storage
- DSPs vs MPUs vs FPGAs
- Cortex-M Series Processors
- Cortex-M3 Processors
- Flash/FRAM Memory
Students Projects
  Nov 27 NO LECTURE: Thanksgiving Break   NO LAB: Thanksgiving Break
26 Dec 2 Special Topics: Communications
- Cameras
- BLE (1)
- BLE (2)
- 802.15.4/ZigBee/6LoWPAN
Students Projects
27 Dec 4 Special Topics: Power
- Power Supplies
- Energy Storage
- Energy Harvesting
- Motor Control
Students Projects
28 Dec 9 Demo & Poster Session
Time: 10:00-12:30
Location: TBD
Students Projects
29 Dec ?? Review and Wrap-Up Dutta Projects
30 Dec 16 Final Exam
Time: 1:30-3:30pm
Location: EECS 1500
Students  


Prerequisites

The curricular prequisites for this class include EECS 270 (Introduction to Logic Design), EECS 280 (Programming and Introductory Data Structures), and EECS 370 (Introduction to Computer Organization). The course bulletin outlines the contents of these courses. In general, students are expected to have a firm grasp on combinational and sequential logic design, be familiar with assembly language programming (for some architecture), be proficient in C programming, and know their way around the elements of a computer. In addition, success in this course will require substantial reading and hacking, and students will need a high degree of patience and determination.


Policies

Honor Code. The Engineering Honor Code applies to all assignments and exams.

Learn Concepts Together through Discussion. Verbal collaboration between members of different groups is permitted for the purpose of helping classmates to understand concepts essential to the labs or providing one another with insights into the best way to approach the in-lab assignments.

Do Your Own Work. Individual assignments (e.g., prelabs, homeworks, and exams) are to be performed on your own. Group assignments (e.g., labs, lab reports, and postlabs) are to be performed only by members of the group. Non-verbal collaboration (e.g. drawing sample schematics on paper or the whiteboard, sharing schematics or code) is not allowed. You may not help debug another group's hardware or software without consent from the lab or course instructor. You are also not allowed to possess, look at, use, or in any way derive advantage from the existence of code, lab reports, or other material prepared in prior years.

Attend Your Registered Lab. You are expected to attend the lab section for which you are registered. If you would like to switch lab sections, but the section you want is full, you must find someone in that lab section to swap positions with you. Once you have agreed on a swap, send email to Matt Smith. All section swaps must be completed before the second week of lab.

Prelabs. Prelabs are due in lab during the week the lab is to start. All prelabs must be turned in within the 20 minutes after the offical start of lab (on the half hour) (to allow for tardiness, printing problems, etc.) or you will only get 50% of the credit otherwise earned. Prelabs more than one week late will earn no credit. For any labs which span multiple weeks, the prelab is due during the first week of that lab. Prelabs are to be done individually unless otherwise specified in the lab itself.

Postlabs. Postlabs are due in lab the week after the last week of that lab. They are due 20 minutes after the start of that lab period. Just like prelabs, late labs earn only 50% of the credit otherwise earned and postlabs which are more than one week late get no credit. Postlabs are to be done by the group unless otherwise specified in the lab itself.

In-Labs. In-labs are due by Friday of the last week of the lab in open lab hours (you are welcome to turn it in before this and most students do). One of the lab instructors must sign your in-lab form by that time for the in-lab to be on time. You should hand in the signed (and dated) in-lab form with your postlab. Late in-labs lose 10% of their value per business day (Monday though Friday not including holidays) they are late. You may only work with your lab group (generally one other person) on your in-lab.


Grading

Item Weight Description
Labs 25% Eight labs: Lab 3 (4%); All other labs (3%).
Project 25% Group project demonstrating understanding of major topics.
Exams 35% Two exams: Midterm (15%); Final (20%).
Homework 10% Four or five homework assignments weighted roughly equally.
Presentation 5% Group presentation to class.

Resources

  1. Combinational Logic Tutorial
  2. Sequential Logic Tutorial
  3. ARMv7 Architecture Reference Manual
  4. ARM Cortex-M3 Technical Reference Manual v2.1
  5. ARM and Thumb-2 Instruction Set Quick Reference Card
  6. ARM Architecture Procedure Call Standard (EABI)
  7. ARM Cortex-M3 Embedded Software Development (AN-179)

Related Courses

  1. Berkeley: EE 145L
  2. Berkeley: EE 149
  3. Colorado: ECEN 5613
  4. Columbia: CSEE 4840
  5. Cornell: ECE 3140
  6. Cornell: ECE 4760
  7. Lund: EDA 385
  8. Stanford: EE 281
  9. UCSC
  10. UCSD: CSE 237d
  11. UNL: CSCE 236
  12. Utah: CS 5785
  13. UW: EE 472

Support

This material is based upon work supported by the National Science Foundation under grant #0964120. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
This course and lab use hardware and software provided by Microsemi Corporation, including the SmartFusion MCU+FPGA development boards and the Libero Gold and Platinum software development tools.