• J. A. Roy and I. L. Markov, ``Partitioning-driven Techniques for VLSI Placement,'' (.pdf) in Handbook of Algorithms for VLSI Physical Design Automation, C. Alpert, D. Mehta and S. Sapatnekar, eds., CRC Press, 2008. (ISBN: 0849372429)
• J. A. Roy, D. A. Papa and I. L. Markov, ``Capo: Congestion-driven Placement for Standard-cell and RTL Netlists with Incremental Capability,'' (.pdf) in Modern Circuit Placement: Best Practices and Results, G.-J. Nam and J. Cong, eds., Springer, 2007. (ISBN: 038736837X)

Papers in Journals and Magazines

• J. A. Roy, A. N. Ng, R. Aggarwal, V. Ramachandran and I. L. Markov, ``Solving Modern Mixed-size Placement Instances,'' to appear in Integration, the VLSI Journal, 2009.
• J. A. Roy, D. A. Papa and I. L. Markov, ``Fine Control of Local Whitespace in Placement,'' to appear in VLSI Design, 2009.
• M. D. Moffitt, J. A. Roy, I. L. Markov and M. E. Pollack, ``Constraint-driven Floorplan Repair,'' ACM Trans. on Design Automation of Electronic Systems vol. 13, no. 4, October 2008.
• J. A. Roy and I. L. Markov, ``High-performance Routing at the Nanometer Scale,'' (.pdf) IEEE Trans. on CAD, vol. 27, no. 6, pp. 1066-1077, 2008.
• J. A. Roy and I. L. Markov, ``ECO-system: Embracing the Change in Placement,'' (.pdf) IEEE Trans. on CAD, vol. 26, no. 12, pp. 2173-2185, 2007.
• J. A. Roy and I. L. Markov, ``Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement'' (.pdf), IEEE Trans. on CAD, vol. 26, no. 4, pp. 632-644, 2007.
• J. A. Roy, S. N. Adya, D. A. Papa and I. L. Markov, ``Min-cut Floorplacement'' (.pdf), IEEE Trans. on CAD, vol. 25, no. 7, pp. 1313-1326, 2006.
• D. B. Motter, J. A. Roy, and I. L. Markov, ``Resolution Cannot Polynomially Simulate Compressed-BFS'' (.pdf), Annals of Mathematics and Artificial Intelligence, vol. 44, no. 1-2, pp. 121-156, May 2005.

Publications In Conference and Workshop Proceedings

• J. A. Roy, F. Koushanfar and I. L. Markov, ``Circuit CAD Tools as a Security Threat,'' Hardware-Oriented Security and Trust Workshop (HOST), pp. 68-69, Anaheim, CA, 2008.
• J. A. Roy, F. Koushanfar and I. L. Markov, ``Protecting Bus-based Hardware IP by Secret Sharing,'' Design Automation Conf. (DAC), pp. 846-851, Anaheim, CA, 2008.
• M. D. Moffitt, J. A. Roy and I. L. Markov, ``The Coming of Age of (Academic) Global Routing,'' Int'l Symposium on Physical Design (ISPD), pp. 148-155, Portland, Oregon, 2008.
• J. Hu, J. A. Roy and I. L. Markov, ``Sidewinder: A Scalable Wire Router Based on ILP,'' Int'l Workshop on System-Level Interconnect Prediction (SLIP), pp. 73-80, Newcastle, England, 2008.
• J. A. Roy, F. Koushanfar and I. L. Markov, ``EPIC: Ending Piracy of Integrated Circuits,'' (.pdf) Design Automation and Test in Europe (DATE), pp. 1069-1074, Munich, Germany, 2008.
• J. A. Roy and I. L. Markov, ``High-performance Routing at the Nanometer Scale,'' (.pdf) Int'l Conf. on Computer-Aided Design (ICCAD), pp. 496-502, San Jose, CA, Nov. 2007.
• J. A. Roy and I. L. Markov, ``ECO-system: Embracing the Change in Placement,'' (.pdf, slides) ASP-DAC, pp.147-152, 2007.
• J. A. Roy, D. A. Papa, A. N. Ng and I. L Markov, ``Satisfying Whitespace Requirements in Top-down Placement,'' (.pdf) Int'l Symp. on Physical Design (ISPD), pp.206-208, San Jose, CA, April 2006.
• J. A. Roy, J. F. Lu and I. L. Markov, ``Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement,'' (.pdf, slides) Int'l Symp. on Physical Design (ISPD), pp. 78-85, San Jose, CA, April 2006.
• J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng and I. L. Markov, ``Capo: Robust and Scalable Open-Source Min-cut Floorplacer,'' (.pdf) Intl. Symposium on Physical Design (ISPD), pp. 224-227, San Francisco, April 2005.
• S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, ``Unification of Partitioning, Floorplanning and Placement,'' (.pdf, slides) Intl. Conf. Computer-Aided Design (ICCAD), pp. 550-557, San Jose, CA, November 2004.

Invited talks, tutorials and discussion panels (w/o proceedings)

• J. A. Roy, D. A. Papa, J. F. Lu, A. N. Ng and I. L. Markov, ``Tool Development For Multi-Million Gate Designs'' (.pdf), workshop on Electronic Design Processes, 2005.

• J. A. Roy, I. L. Markov and V. Bertacco, ``Restoring Circuit Structure from SAT Instances'', (.pdf, slides), IWLS, pp. 361-368, Temecula Creek CA, June 2004.
• J. A. Roy and I. L. Markov, ``On Sub-optimality and Scalability of Logic Synthesis Tools,'' (.pdf, slides) IWLS, Laguna Beach, CA, May 2003.