Welcome to Saurabh's Home Page

Always Under Construction !!!!!!

I was a graduate student at the University of Michigan, Electrical Engineering and Computer Science Department. I graduated from UoM in 2004 and joined the EDA company Synplicity Inc in their ASIC division. I am currently working in their Central Technology Group.

My research advisor is Prof Igor Markov.

my picture

Links

Resume  (.ps)      (.pdf)

Contact Information :

Saurabh Adya,
Synplicity Inc.,
600 W. California Avenue,
Sunnyvale, CA 94086

Telephone: (408) 215 6074 (O)
Email: sadya@eecs.umich.edu

Publications

In Journals :

[5] S. N. Adya and I. L. Markov, "On Whitespace and Stability in Physical Synthesis", to appear in Integration the VLSI Journal, 2005

[4] J. A. Roy, S. N. Adya, S. Chaturvedi, D. Papa and I. L. Markov, "Min-cut Floorplacement", to appear in IEEE Trans. on CAD, 2005

[3] S.N. Adya, M. Yildiz, I. L. Markov, P. G. Villarrubia, P.N. Parakh and P. H. Madden, "Benchmarking for Large-scale Placement and Beyond", in IEEE Trans. on CAD, vol. 23(4), April, 2004, pp. 472-487.

[2] S.N. Adya, I.L. Markov, "Combinatorial Techniques for Mixed-size Placement", in ACM Trans. on Design Automation of Electronic Systems, vol. 10, no. 5, January 2005

[1] S.N. Adya, I.L. Markov, "Fixed-outline Floorplanning : Enabling Hierarchical Design", IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135 


In Conferences :

[9] J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng and I. L. Markov, "Capo: Robust and Scalable Open-Source Min-cut Floorplacer", in International Symposium on Physical Design (ISPD), pp. 224-226, San Fransisco, 2005 (invited)

[8] H. H. Chan, S. N. Adya, and I. L. Markov, "Are Floorplan Representations Useful in Digital Design?", in International Symposium on Physical Design (ISPD), San Fransisco, 2005, pp. 129-136

[7] S. N. Adya, S. Chaturvedi, J. A. Roy, D. Papa and I. L. Markov, " Unification of Partitioning, Floorplanning and Placement", in International Conference of Computer Aided Design (ICCAD), San Jose, 2004, pp. 550-557

[6] D. Papa, S. N. Adya and I. L. Markov, "Constructive Benchmarking for Placement", Great Lakes Symposium on VLSI (GLSVLSI), 2004, pp. 113-118.

[5] S.N. Adya and I.L. Markov, "On Whitespace and Stability in Mixed-size Placement and Physical Synthesis", International Conference on Computer Aided Design (ICCAD), pp. 311-318 San Jose, 2003.

[4] S.N. Adya, M. Yildiz, I. L. Markov, P. G. Villarrubia, P. N. Parakh and P. H. Madden, "Benchmarking for Large-scale Placement and Beyond", International Symposium on Physical Design (ISPD), pp. 95-103 Monterey, 2003 (invited).

[3] S.N. Adya, I.L. Markov, P.G. Villarrubia, "Improving Min-cut Placement for VLSI Using Analytical Techniques", IBM ACAS Conference, pp. 55-62, Austin, 2003.

[2] S.N. Adya, I.L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement", International Symposium of Physical Design(ISPD), pp.12-17, San Diego,2002. 

[1] S.N. Adya, I.L. Markov, "Fixed Outline Floorplanning Through Better Local Search", International Conference of Computer Design (ICCD), pp.328-334, Austin, 2001

 
Software Releases

  Parquet Floorplanner

  UMICH/UCLA Physical Design Tools (Capo Standard Cell Placer)

  Placement Utilities

  Mixed-size Placement Benchmarks (ISPD'02)

  Mixed-size Placement Benchmarks (ICCAD'04)

  Grid Benchmarks
 

Courses

Fall '00
    EECS 527(CAD for VLSI)
    EECS 470(Computer Architecture)

Winter '01
    EECS 627(Advanced VLSI Design)
    EECS 586(Design and Analysis of Algorithms)

Fall '01
    EECS 570(Parallel Computer Architecture)
    EECS 571(Real Time Systems)

Winter '02
    EECS 492(Intro to Artificial Intelligence)
    EECS 451(Digital Signal Processing)

Fall '02
    EECS 587(Parallel Algorithms)

More Later !!!