My primary area of interest is hardware reliability. I am currently working on the design of a reconfigurable processor architecture StageNet with reliability as the primary design criteria. I have also contributed to several other on-going/completed reliability related projects:
Scan chain is a very ubiquitous architecture used in VLSI testing process. Unfortunately, scanning in of test vectors is a very power hungry step. Majority of this power is dissipated as a result of the high switching activity in the scan chain flip flops. In this work I proposed a novel architecture for the scan chain that involves optimal connection strategy between consecutive flip flops that reduces the overall power dissipation.
Automatic test pattern generation is a well studied research area. And over the years, PODEM and FAN have been accepted as the de-facto algorithms for this problem. But, these algorithms are limited to handling SSL fault model. With the growing reliability concerns, it is necessary to approach this problem in a more generic manner. In this work I suggested mapping of the test pattern generation problem to a single SAT (satisfiability) problem. Solving which would give us a minimal and complete set of test vectors. The method had a flexibility to support DSL (Double Stuck at Line) and higher fault models.
Even though this approach was very interesting, the running time and memory requirement of the SAT solver was prohibitively expensive making this technique impractical.
Starting with my summer internship at Technical University of Munich, Germany, I got interested in the field of optimization and its potential to solve engineering problems. Over the time, I have learned both traditional as well as statistical techniques for optimization and applied them to a variety of problems. Some of the optimization techniques that I have used are Normal-Boundary Intersection, Recursive Knee approach and Genetic algorithms. Problems solved using these techniques: