Negative differential resistances (NDRs) can cause problems for SPICE-like circuit simulators. Circuit simulators usually employ a variant of the Newton-Raphson algorithm to solve non-linear circuit equations. Even though Newton-Raphson type of methods are quadratically convergent, they may get stuck at local maxima or minima and fail to find the actual solution. NDR characteristics in devices can increase the chances of occurrence of this type of failure both during DC and transient simulation. We have dealt with this problem for resonant tunneling diode (RTD) circuits by introducing several techniques that can be termed as 'convergence aids'. Initially we studied the problems associated with the piece-wise-linear device models and overcame them using a 'forced-convergence' routine. More recently, we incorporated a physics-based RTD model into our version of SPICE3f5 and comprehensively studied the associated DC and transient simulation problems. Even though the convergence problems are much less frequent compared to the piece-wise-linear model because of the function being continuously differentiable, there are plenty of cases where the NDR characteristics can cause DC and transient convergence failures even after the application of Gmin or Source-stepping. We have developed specific continuation techniques for RTDs and other NDR devices that can lead to much better convergence performance. Transient simulation problems like 'time-step too small' and convergence to the wrong operating point are also quite common for NDR circuits. We have solved such problems by means of time-step adjustment techniques.
Even though SPICE is an extremely accurate simulation tool, it can only be considered to be accurate under quasi-static conditions. When signal rise times are extremely small and interconnect lengths are comparable to the signal wavelengths, quasi-static assumptions are not valid, and full-wave simulation has to be carried out. RTDs are the fastest switching semiconductor devices currently available. RTDs, in conjunction with three terminal devices like HBTs or HFETs having fmax in the neighborhood of several hundred gigahertz, can be used to design ultra-high-speed digital circuits. The functionality of such circuits should be verified using full-wave simulation methods. The focus of our current circuit simulation research activities is full-wave time-domain simulation of RTD circuits. We are exploring various time-domain simulation techniques like the finite-difference time-domain (FDTD) and the transmission line matrix (TLM) methods for this purpose.
We are examining the theoretical and experimental aspects of genetic algorithms for optimization of various physical design automation problems, such as placement, routing, floor planning, and PLA folding. By exploiting the parallel optimization capabilities of genetic algorithms, we have developed CAD tools for the parallel placement of standard and macro cells. At present, in industry, the typical CAD program design environment consists of a network of workstations. We have, therefore, developed tools that run efficiently (with linear speedup) on a network of Sun and DEC workstations to accelerate the placement phase significantly, while providing a layout quality similar to that of simulated annealing. Our objective function includes circuit speed/performance constraints and additionally, we are modeling other issues namely, reliability, perfomability, routability, and testability to include them in our cost function. Special attention is paid to meet the power, ground (especially in analog layouts), and clock skewing specifications.
In terms of hardware CAD acceleration, we have designed a VLSI chip for acceleration of the wire routing phase in automatic VLSI and PCB layout design. We have developed a unique wraparound hexagonal mesh architecture that can perform concurrent multi-layer maze routing. Previous research in this area, including IBMs wire routing machine (WRM) and NECs twisted torus machine could only route a layer at a time and failed to route concurrently in multiple layers. We are planning to redesign our processor elements for accelerating other commonly used multi-layer channel and global routing algorithms so as to eventually construct a general-purpose routing machine.