Power Estimation and Reduction for VLSI

The increasing demand for portable computing and wireless communication, as well as other applications, has necessitated low power consumption. Even when power is not a major constraint in other mains-operated applications, the issue of low power design is becoming critical: the continuing decrease in device feature size and the corresponding increase in the density of the chips might result in difficulty in providing adequate cost-effective cooling system. Excessive power dissipation in integrated circuits might also cause overheating, which degrades performance and reliability. Low power consumption can be obtained at various levels: technology, circuit, logic, architecture and algorithm. The research on low power design at NDR group is at logic level, which basically consists of two tasks:

• Power Estimation
• Power Reduction

Transition Density Based Power Estimation

Accurate and efficient power estimation in the design phase is important in order to meet the power specifications. The power consumption in CMOS circuits consists of three components:

1. static consumption
2. short-circuit consumption
3. dynamic consumption

\begin{equation} \label{eqn:density} D(x)= \lim_{T \to \infty} \frac{n_x(T)}{T} \end{equation} Considering a combinational network $\mathcal{C}$ with inputs $x_i$, $i=1$, $2$, $...$, $n$ with transition densities $D(x_i)$, then the transition densities at its outputs $y_i$, $j=1,...m$, are given by: \begin{equation} \label{eqn:propagation} D(y_j)= \sum_{i=1}^{m} P(\frac{\partial y_i}{\partial x_i}) D(x_i) \end{equation} where $P(\frac{\partial y_i}{\partial x_i})$ is the probability of the boolean difference of $y_j$ with respect to $x_i$.

A transition density simulator, PowerSim, is developed at the NDR group. The simulator reads in the netlist of circuit, levelizes the netlist and propagates the signal probabilities and transition densities to primary outputs. The power consumption is the sum of power consumption at every node which is the product of transition density and node capacitance. Without reconvergent paths, the simulator gives accurate result. In the presence of convergent paths, the correlation between nodes must be taken into account. BDD-based signal probability computation gives accurate result. However, the complexity of BDD solution is exponential in worst case. This is overcome by using limited depth reconvergent path analysis. Only when logic depth of reconvergent paths is greater than l, spatial correlation introduced by reconvergent paths is taken into account. In our program, \emph{l}=2 is chosen because of trade-off of accuracy and computation time. PowerSim is run on MCNC benchmark circuits and error is within 10% in most of cases compared to logic level simulation.

Rewiring Power Reduction

Rewiring power reduction employs local transformations to reduce the transition activities in a CMOS combinational circuit. It adds redundant \emph{``cold''} connections or gates of low activities to \emph{``hot''} gates to reduce the transition activities of the \emph{``hot''} gates. The area and delay overhead introduced by rewiring is limited to meet with area and speed constraints. Rewiring can be used as re-synthesis in most of cases.

Implementation of rewiring power reduction consists of:

1. Selection of a gate $g_l$ with low transition density Gates with high transition densities do not help reduce total transition densities and introduce unnecessary delay.
2. Selection of logic value $v$ at gate $g_l$
3. Forward/backward implication of value $v$ at $g_l$
4. Backward propagation of implied unobservabilities Backward propagation tries to find the least deep target gate so that only minimum number of signals are added into the circuit.
5. Unnecessary redundancy removal Not all redundancy introduced helps reduce power consumption.
6. Delay evaluation The reduction of power should not introduce significant extra delay. Delay constraint can be specified by user input.