This is an obsolete version of P. Mazumder's Publications. Up to date Resume is available in pdf and postscript form. This page was designed in 1997. [PostScript ] [PDF]

Books

1. P. Mazumder and K. Chakraborty, "Testing and Testable Design of Random-Access Memories," Kluwer Academic Publishers, 1996.
2. P. Mazumder, "Models and Techniques for VLSI Routing," (in preparation) .

3. P. Mazumder and E. Rudnick, "Genetic Algorithms for VLSI Design, Layout, and Test Automation," Prentice Hall, 1998.

4. R. Rajsuman and P. Mazumder, "Semiconductor Memories: Testing and Reliability," Computer Science Press, to appear (edited version).

5. K. Chakraborty and P. Mazumder, "Fault Tolerance and Reliability Aspects of Random-Access Memories," in preparation.

Text Book Chapters

1. K. Shahookar and P. Mazumder, "Standard Cell Placement and the Genetic Algorithm," Book chapter in "Advances in Computer-Aided Engineering Design, Vol. II," I. N. Hajj (editor), Jai Press, Greenwich, Connecticut, 1990, pp. 159-234.
2. W. K. Fuchs, M. F. Chang, S. Y. Kuo, P. Mazumder and C. B. Stunkel, "The Impact of Parallel Architecture Granularity on Yield," Book chapter in "Designing for Yield", Moore, Strowjas and Maly (editors), Adam Hilger Publisher, 1988.
3. P. Mazumder and J. H. Patel, "Parallel Testing of Parametric Faults in DRAM", in "Advanced Research in VLSI: Design and Applications of Very Large Scale Systems", Leighton and Allen (editors), MIT Press, 1988. (Presented at the 5-th Massachusetts Institute of Technology Conference on VLSI).
4. P. Mazumder, "Design of a Fault-Tolerant DRAM with New On-Chip ECC," Book Chapter in "Defects and Fault Tolerance in VLSI Systems," I. Koren (editor), Plenum Press, 1989.
5. H. Chan and P. Mazumder, "A Systolic Architecture for High-Speed Hypergraph Partitioning Using a Genetic Algorithm," Book Chapter in "Progress in Evolutionary Computation", Vol. 956, Springer-Verlag, Heildelberg, 1995, pp. 109-126.

Book Reviews

1. J.V. Oldfield, J.P. Gray, T.A. Kean, and R.C. Dorf, Field-Programmable Gate Arrays for Implementation and Rapid Prototyping of Digital Systems, John Wiley and Sons, Inc., New York.
2. John Beetam, Computer Architectures, Aksen Associates Inc. Publishers, California. The Science and Technology of Microelectronic Processing, Saunders College Publishing, Pennsylvania.
3. Dhiraj Pradhan, Fault-Tolerant System Design, Prentice Hall, New Jersey.
4. Price, Introduction to VLSI Design, Prentice Hall, New Jersey. C.P. Ravi Kumar, Computer-Aided Design for VLSI Systems, Kluwer Academic Publishers, Massachussetts.
5. Fu, Neural Networks in Computer Intelligence, Prentice Hall, New Jersey.
6. P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design Applications, Prentice Hall, New Jersey.
7. R. Karri, Automatic Synthesis of Fault-tolerant VLSI Systems, Kluwer Academic Publishers, Massachussetts.
8. A. S. Sedra and K. C. Smith, "SPICE Simulation: Microelectronics Circuits," Prentice Hall.

Journal Publications

CAD
Testing
Fault Tolerance
Ultrafast Circuits
Miscellaneous
Under Review

Physical Design of VLSI Systems

1. K. Shahookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement with Meta-Genetic Parameter Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 5, May 1990, pp. 500-511.
2. R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 10, Oct. 1990, pp. 1096-1112.
3. J. Yih and P. Mazumder, "A Neural Network Design for Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 12, Dec. 1990, pp. 1265-1271.
4. K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques", ACM Computing Surveys, Vol. 23, No. 2, Jun. 1991, pp. 143-220 (Also, translated in Japanese and published in "bit: Computer Science '91", Kyoritsu Shuppan Co., Ltd., Tokyo).
5. P. Mazumder, "Planar Decomposition Strategies for Quadtree Data Structure," Journal of Computer Vision, Graphics, and Image Processing, Academic Press, Jun. 1987, pp. 258-274.
6. H. M. Chan, P. Mazumder and K. Shahookar, "Macro-Cell and Module Placement by Genetic Optimization with Bit-Map Represented Crossover Operators," Integration: An International VLSI Journal, Dec. 1991, pp. 49-77.
7. P. Mazumder, "Layout Optimization for Yield Enhancement in On-Chip VLSI/WSI Parallel Processing," IEE Proceedings-E: Computers and Digital Techniques. Vol. 139, No. 1, Jan. 1992, pp. 21-28.
8. S. Mohan and P. Mazumder, "WOLVERINES: A Distributed Standard Cell Placement Tool," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept. 1993, pp. 1312-1326.
9. K. Shahookar, W. Khamisani, P. Mazumder, S.M. Reddy, "Genetic Beam Search for Gate Matrix Placement," IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2, Mar. 1994, pp. 123-128.
10. H. Esbensen and P. Mazumder, "SAGA: Unification of Genetic Algorithm with Simulated Annealing and Its Application to Macro-Cell Placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
11. R. Venkateswaran and P. Mazumder, "DA Techniques for PLD and FPGA Based Systems," Integration: An International VLSI Journal, Vol. 17, Dec. 1994, pp. 191-240.
12. R. Venkateswaran and P. Mazumder, "Highly Parallel Grid Graph Based Routing Algorithm," IEE Proceedings-E: Computers and Digital Techniques.
13. H. Esbensen and P. Mazumder, "Viking: Macro-cell Placement by Genetic Algorithm," IEE Proceedings-E: Computers and Digital Techniques.

Testing of VLSI Systems

1. P. Mazumder, J. H. Patel and W. K. Fuchs, "Methodologies for Testing Embedded Content-Addressable Memories," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 1988, pp. 11-20.
2. P. Mazumder, "Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-Access Memory," IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp. 933-942.
3. P. Mazumder and J. H. Patel, "Parallel Testing of Pattern-Sensitive Faults in Random-Access Memory," IEEE Transactions on Computers, Vol. 38, No 3, Mar. 1989, pp. 394-404.
4. P. Mazumder and J. H. Patel, "An Efficient Built-In Self-Testing Algorithm for Random-Access Memory," IEEE Transactions on Industrial Electronics (Special Issue on Testing) Vol. 36, No. 3, May 1989, pp. 394-407.
5. J. S. Yih and P. Mazumder, "Circuit Behavior Modeling and Compact Testing Performance Evaluation," IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, Jan. 1991, pp. 62-65.
6. P. Mazumder and J. H. Patel, "A Comprehensive Study of Random Testing for Embedded RAMs Using Markov Chains," Journal of Electronic Testing: Theory and Applications, Vol. 3 No. 4, Nov. 1992, 235-250.
7. S. Mohan and P. Mazumder, "Analytical and Simulation Studies of Failure Modes in SRAM's Using High-Electron Mobility Transistors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 12, No. 12, Dec. 1993, pp. 1885-1896.
8. P. Mazumder and J. P. Hayes, "Testing and Improving the Testability of Multimegabit Memories," IEEE Design and Test of Computers, March 1993, pp. 6-7.
9. K. Chakraborty and P. Mazumder, "Technology and Layout Related Testing in Static Random-Access Memories," Journal of Electronic Testing: Theory and Applications, Aug. 1994.
9. K. Chakraborty and P. Mazumder, "New March Tests for Multiport RAM Devices," Journal of Electronic Testing: Theory and Applications, Aug. 2000.

Fault Tolerance of VLSI Systems

1. P. Mazumder, J. H. Patel and J. A. Abraham, "A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in Dynamic Random-Access Memory," IEEE Journal of Solid-State Circuits Vol. 25, No. 3, Jun. 1990, pp. 866-870.
2. P. Mazumder and J. Yih, "Restructuring of Square Processor Arrays by Built-in Self-Repair Circuit," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept. 1993, pp. 1255-1265.
3. P. Mazumder, "A New On-Chip ECC Circuit for Correcting Soft Errors in DRAMs with Trench Capacitors," IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1623-1633.
4. R. Venkateswaran, P. Mazumder and K. G. Shin, "On Restructuring of Hexagonal Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 12, Dec. 1992, pp. 1574-1585.
5. P. Mazumder and J. Yih, "A New Built-in Self-Repair Approach to VLSI Memory Yield Enhancement by Using Neural-Type Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 1, Jan. 1993, pp. 124-136.
6. P. Mazumder, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit," IEEE Transactions on Computers, Vol. 42, No. 12, December 1993, pp. 1453-1468.
7. M.D. Smith and P. Mazumder, "Analysis and Design of Hopfield-type Network for Built-in Self-repair of Memories," IEEE Transactions on Computers, Vo, 45, No. 1, January 1996.
8. P. Mazumder, "Built-In Self-Repair for WSI Hexagonal Processor Arrays," IEE Proceedings-E: Computers and Digital Techniques.

VLSI Circuit Design

1. P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. I. Haddad, "Digital Circuit Applications of Resonant-Tunneling Devices," Proceedings of the IEEE, Vol. 86, No. 4, April 1998, pp. 664-686. (Invited Paper)
2. J. P. Sun, G. I. Haddad, P. Mazumder, and J. N. Schulman, "Resonant Tunneling Diodes: Models and Properties," Proceedings of the IEEE, Vol. 86, No. 4, April 1998, pp. 641-661. (Invited Paper)
3. S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and S. Sung, "Ultrafast Pipelined Adders Using Resonant Tunneling Transistors," IEE Electronics Letters, Vol. 27, No. 10, May 1991, pp. 830-831.
4.
5. P. Mazumder, "Evaluation of On-Chip Static Interconnection Networks," IEEE Transactions on Computers, C-36, Mar. 1987, pp. 365-369.
6. S. Mohan, P. Mazumder, G.I. Haddad and W. L. Chen, "Pico Second Pipelined Adder Using Three-Terminal NDR Devices," IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2, Mar. 1994, pp. 104-110.
7. R. Venkateswaran and P. Mazumder, "Design of a Coprocessor for Accelerating the Maze Routing in VLSI and PCB Layouts," IEEE Transactions on VLSI Systems, Mar. 1993, Vol. 1, No. 1, pp. 1-14.
8. S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and S. Sung, "Logic Design Based on Negative Differential Resistance Characteristics of Quantum Electronic Devices," IEE Proceedings-G: Electronic Devices, Vol. 140, No. 6, Dec. 1993, pp. 383-391.
1. E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, "Multivalued Multiplexer Design Using Resonant Tunneling Devices and Heterojunction Bipolar Transistors," IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, August 1996, pp. 1151-1156.
2. E. Chan, M. Bhattacharya, P. Mazumder and G.I. Haddad, "Mask Programmable Multi-Valued Logic Gate Arrays Using RTDs and HBTs," IEE Proceedings-E: Computers and Digital Techniques, Vol. 143, No. 5, October 1996, pp. 289-294.
3. S. Mohan, J.P. Sun, P. Mazumder and G. I. Haddad, "Device and Circuit Models for Resonant Tunneling Devices for Circuit Simulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 140, No. 6, June 1995, pp. 653-662.
4. P. Mazumder, J.P. Sun, S. Mohan and G.I. Haddad, "DC and Transient Simulation of Resonant Tunneling Devices in NDR-SPICE," Institute of Physics, No. 141, Sept. 1994, pp. 867-872
5. G. I. Haddad and P. Mazumder, "Tunneling Decices and Applications in High Functionality/Speed Digital Circuits," Solid State Electronics, Vol. 41, No. 10, Oct. 1997, pp. 1515-1524.
6. P. Mazumder, "An Economical Design of Programmable Seven Segments to Decimal Decoder," Electronic Design News, Apr. 1987, pp. 222-224, (Design Ideas Prize Winner).

Miscellaneous

1. P. Mazumder, "New Switched-Mode CSMA/CD Protocol That Improves the Performance of Delay-Critical Traffic," Computer Systems - Science and Engineering.
2. P. Mazumder, "Satellite Communications versus Submarine Cables for Long Distance Links," IETE Journal - A Special Issue on TV Communication in India, 1976 (Best Student Paper Award Winner).

Journal Papers under Review

1. H. Esbensen and P. Mazumder, "A Genetic Algorithm for the Steiner Routing Problem in a Graph," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ({\em will be accepted pending some changes}).
2. K. Chakrabaorty, A. Gupta and P. Mazumder, "BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM Compiler," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
3. A. Gupta, K. Chakraborty and P. Mazumder, "FTROMGEN - A Fault-Tolerant Self-Repairable ROM Compiler," IEEE Transactions on VLSI Systems.
4. R. Venkateswaran and P. Mazumder, "Parallel Algorithms for Multi-layer Detailed Routing and Steiner-tree Generation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ({\em will be accpeted pending some changes}).
5. K. Chakraborty and P. Mazumder, "An Efficient Bus-layout based Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
6. K. Chakraborty and P. Mazumder, "Efficient Marching Algorithms for Testing Multi-port Memories at the Board Level," IEEE Transactions on Computers.
7. A. Gonzalez and P. Mazumder, "A Signed-Digit Adder Using RTDs and CMOS Devices," IEEE Journal of Solid-State Circuits.
8. S. Kulkarni, P. Mazumder and G. I. Haddad, "A 32-bit RTD-based Nano-pipelined Correlator for Ultra-fast Communication Systems," IEE Proceedings-E: Computers and Digital Techniques.
9. S. Kulkarni and P. Mazumder, "Bistable Logic Circuits using RTDs and CMOS," IEEE Transactions on Computers.
10. M. Bhattacharya and P. Mazumder, "Analysis of HBT and RTD based Circuits," International Journal of High-Speed Electronics and Systems.
11. P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, "Design and Simulation of Resonant-Tunneling Diode Circuits," IEEE Computer Magazine.
12. P. Mazumder and S. Mohan, "Optimization of Multi-state Memories," IEEE Transactions on Circuits and Systems.
13. T. Ueura and P. Mazumder, "On the Stability of RTD based Monostable-to-Bistable Transition Circuits," IEEE Transactions on Circuits and Systems.

Rigorously Reviewed Conference Publications

1. P. Mazumder, J. H. Patel and W. K. Fuchs, "Design and Algorithms for Parallel Testing of Random-Access and Content-Addressable Memory," Proc. ACM/IEEE 24th Design Automation Conference, Florida, Jun. 1987, pp. 688-694 (nominated for the Best Paper Award).
2. P. Mazumder, "Evaluation of Three Interconnection Networks for CMOS VLSI Implementation," Proc. IEEE International Conference on Parallel Processing, St. Charles, Illinois, Aug. 1986, pp. 200-207.
3. P. Mazumder and J. H. Patel, "Methodologies for Testing Embedded Content-Addressable Memories," Proc. IEEE 17th International Symposium on Fault-Tolerant Computing, Jul. 1987, Pittsburgh, Pennsylvania, pp. 270-275.
4. P. Mazumder, "A Novel Universal Seven-Segment-to-Decimal Decoder," Proc. IEEE 6th Biennial University, Government and Industry Microelectronics (UGIM) Conference, Alabama, Jun. 1985.
5. P. Mazumder and J. H. Patel, "An Efficient Built-In Self-Testing Algorithm for Random-Access Memory," Proc. IEEE International Test Conference, Sep. 1987, pp. 1072-1077.
6. P. Mazumder and J. H. Patel, "A Novel Fault-Tolerant Design of Testable Dynamic Random-Access Memory," Proc. IEEE International Conference on Computer Design, New York, Oct. 1987, pp. 306-309.
7. P. Mazumder, "Planar Topologies for Tree Representation," Proc. 14th Annual Conference on Numerical Mathematics and Computing Science, Winnipeg, Canada, Sep. 1984.
8. P. Mazumder "On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional DRAMs" Proc. IEEE International Test Conference, Sep. 1988, Washington, pp. 279-288.
9. P. Mazumder, "A New Strategy for Octtree Representation of Three-Dimensional Objects," Proc. IEEE Conference on Computer Vision and Pattern Recognition, Jun. 1988, Ann Arbor, pp. 270-275.
10. P. Mazumder, "An Efficient Design of Embedded Memories for Random Pattern Testability," Proc. IEEE International Conference on Wafer Scale Integration, Jan. 1989, San Francisco, pp. 230-237.
11. P. Mazumder and J. Yih, "Fault-Diagnosis and Self-Repairing of Embedded Memories by Using Electronic Neural Network," Proc. IEEE 19th Fault-Tolerant Computing Symposium, Chicago, Jun. 1989, pp. 270-277.
12 J. Yih and P. Mazumder, "A Neural Network Design for Circuit Partitioning," Proc. ACM/IEEE 26th Design-Automation Conference, Las Vegas, Jun. 1989, pp. 406-411.
13 R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," Proc. IEEE International Conference on Computer-Aided Design, Nov. 1989.
14 K. Shahookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement with Meta-Genetic Parameter Optimization," Proc. IEEE European Design Automation Conference, Glasgow, England, Mar. 1990, pp. 370-378.
15. R. B. Panwar and P. Mazumder, "A Parallel Karmarkar Algorithm Implemented on Orthogonal Tree Networks," Proc. International Parallel Processing Conference, Aug. 1990, Vol. 3., pp. 270-273.
16. P. Mazumder and J. Yih, "Built-In Self-Repair Techniques for Yield Enhancement of Embedded Memories," Proc. IEEE International Test Conference, Sep. 1990, pp. 833-841.
17. S. Mohan and P. Mazumder, "Wolverine: A Distributed Standard Cell Placement Tool," Proc. IEEE European Design Automation Conference, Hamburg, Germany, Sep. 1992.
18. R. Venkateswaran, P. Mazumder and K. G. Shin, "On Restructuring of Hexagonal Processor Arrays," Intl. Conf. on Defect and Fault Tolerance in VLSI Systems, Nov 1991
19. P. Mazumder and J. Yih, "Processor Array Self-Reconfiguration by Neural Networks," Intl. Wafer Scale Integration, Jan. 1992.
20. S. Mohan and P. Mazumder, "Fault Characterization and Testing of GaAs Static Random-Access Memories using High-Electron Mobility Transistors," Proc. on Intl. Test Conference, Oct. 1991, Nashville, pp. 665-674.
21. K. Shahookar, P. Mazumder and S. M. Reddy, "Gate Matrix Placement by Genetic Algorithm Combined with Beam Search," Proc. on IEEE VLSI-93, Bombay, India, Jan. 1993.
22. P. Mazumder, "An Integrated Built-in Self-Testing and Self-Repair of Hexagonal Arrays," Proc. on International Test Conference, Baltimore, Sep. 1992.
23. W.L. Chen, G.I. Haddad, G.O. Munns, S. Mohan and P. Mazumder, "InP-Based Quantum Effect Devices: Device Fabrication and Application in Digital Circuits," Proc. on International Electron Device and Material Symposium, Taipei, Taiwan, Nov. 1992.
24. K. Shahookar and P. Mazumder, "Genetic Min-cut Partitioning," Proc. on VLSI 1995, New Delhi, India.
25. R. Venkateswaran and P. Mazumder, "Highly Parallel Grid Graph Based Routing Algorithm," European Design Automation Conference, (submitted)
26. H. Esbensen and P. Mazumder, "SAGA: Unification of Genetic Algorithm with Simulated Annealing and Its Application to Macro-Cell Placement," Proc. on IEEE VLSI-1994, Calcutta, India, Jan. 1994.
27. H. Esbensen and P. Mazumder, "A Genetic Algorithm for the Steiner Routing Problem in a Graph," Proc. on European Design Automation Conference, Mar. 1994, Paris.
28. E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, "Multivalued Multiplexer Design Using Resonant Tunneling Devices and Heterojunction Bipolar Transistors," Proc. on Government Microciruits Application Conference, Nov. 1994, San Diego.
29. S. Mohan, P. Mazumder and G. I. Haddad, "NDR SPICE: A Circuit Simulator for Resonant Tunneling Devices," Proc. on International Compound Semiconductors Conference, Sep. 1994, San Diego.
30. M.D. Smith and P. Mazumder, "Analysis and Design of Hopfield-type Network for Built-in Self-repair of Memories," Proc. on Government Microciruits Application Conference, Nov. 1994, San Diego.
31. E. Chan, P. Mazumder and G.I. Haddad, "Mask Programmable Multi-Valued Logic Gate Arrays Using RTDs and HBTs," Proc. on Intl. Electron Devices Meeting, Dec. 1994.
2. S. Mohan, P. Mazumder and G. I. Haddad, "A New Circuit Simulator for Negative Resistance Devices," Proc. on Intl. Electron Devices Meeting, Dec. 1994.
32. S. Kulkarni, P. Mazumder and G. I. Haddad, "A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices," International Conference on Micro-nanotechnology for Space Applications, Oct. 1995.
33. S. Kulkarni, P. Mazumder and G. I. Haddad, "A High-speed 32-bit Parallel Correlator for Spread Spectrum Communication," Ninth International Conference on VLSI Design, Jan. 1996.
34. H. Chan and P. Mazumder, "Genetic Algorithms and Classifier Systems," Proc. on AAAI Conference, Nov. 1994, Sydney, Australia.
35. P. Mazumder, K. Saluja and M. Franklin, "Technology Testing of DRAMs," IEEE Memory Testing Symposium, Aug. 1995, San Jose.
36. K. Chakraborty and P. Mazumder, "An Efficient, Bus-layout Based Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards," International Conference on Computer-Aided Design, Santa Clara, California, Nov. 1996.
37. A. Gonzalez and P. Mazumder, "High-speed Signed-digit Adder Using RTDs and MOSFETs," Proc. on Government Microcircuits Applications Conference, Las Vegas, March 1997.
38. G.I. Haddad and P. Mazumder, "Resonant Tunneling Devices and Their Applications," Proc. on Symposium of Heterostructure Devices, Japan, Aug. 1996.
39. P. Mazumder, "Multivalued Logic Design Using HBTs and RTDs," Proc. on Frontiers in Electronics, Tenerife, Spain, Jan. 1997.
40. K. Chakraborty and P. Mazumder, "Efficient Marching Algorithms for Testing Multiport Memories at the Board Level," Proc. on European design and Test Conference, Paris, France, Mar. 1997.
41. P. Mazumder, "Parallel VLSI-Routing Models for Polymorphic Processors Array," Proc. on IEEE VLSI 1997 Conference, Jan. 1997.
42. P. Mazumder, "Ultrafast Circuits and Systems Using Quantum Devices," Proc. on Frontiers in Electronics, Tenerife, Spain, Jan. 1997.
43. P. Mazumder and G.I. Haddad, "Digital Applications of NDR Devices," Proc. on Advanced Heterostructure Devices, Kona, Hawaii, Dec. 1996.
44. P. Mazumder, "Genetic Algorithms for Standard and Macro-cell Placement," (invited) Proc. on INFORMS, May 1997, San Diego.
45. P. Mazumder, "Ultrafast Circuit Design using Quantum Electronic Devices," (invited) Proc. of European Circuit Theory and Design Conference, August 1997, Budapest, Hungary.
46. A. Gonzalez and P. Mazumder, "Multivalued Signed Digit Adder Using RTD and CMOS," Proc. of Advanced Research in VLSI Conference, Sep. 1997, Ann Arbor.
47. P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, "Design and Simulation of Resonant Tunneling Diode Circuits," Proc. of IEEE VLSI 1998 Conference, Jan. 1998, Chennai, India.
48. S. Kulkarni and P. Mazumder, "Full Adder Circuit Design Using RTDs and MOSFETs," Proc. of Govt. Microcircuit Applications Conference, Mar. 1998, Arlington.
49. P. Mazumder, "Quantum Electronic Circuit Design," Proc. of Quantum Functional Devices, Nov. 1997, Washington D.C.
50. P. Mazumder, "Testing and Testable Design of SRAMs and DRAMs (Invited)," Proc. on Intel Test Symposium, Mar. 1997, Santa Clara.
51. P. Mazumder and A. Seabaugh, "Quantum Electronic Devices: Principles, fabrication and Applications," invited tutorial, GOMAC Tutorial, Mar. 1998, Arlington.
52. M. Bhattacharya and P. Mazumder, "Noise Margin of Threshold Logic Gates for Resonant Tunneling Diodes," Proc. of 8th Great Lakes Symposium on VLSI, Lafayette, Feb. 1998.
53. P. Mazumder, "Built-in self-repair of VLSI Chips Using Neural-type Adaptive Circuits," Invited, Proc. of SPIE (Application of Neural Networks, Fuzzy Systems, and Evolutionary Computations in Electronic CAD), July 1998.
54. P. Mazumder, "Failure Modes in Deep-Submicron CMOS Memories," Invited for Embedded Tutorial, Proc. on VLSI Test Symposium, Monterey, Mar. 1998.
55. N. Deb, J. Xiong, M. Bhattacharya, S. Kulkarni and P. Mazumder, "Analysis of Switching Speed and Power Dissipation of RTD-CMOS Bistable Logic Gates," Proc. of Silicon Nanoelectronics, June 1998.
56. N. Deb and P. Mazumder, "Analysis of Failures in Deep Submicron Static RAM Cells," (submitted to the International Test Conference, Oct. 1998).
57. G. Mittal and P. Mazumder, "Analysis of Coupling Between Bit Lines of Deep Submicron Adjoining SRAM Cells," (submitted to the International Test Conference, Oct. 1998).
58. K. Chakrabaorty and P. Mazumder, "BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM Compiler," International Test Conference, Oct. 1998.

Technical Reports and Memoranda

1. P. Mazumder and J. H. Patel, "Parallel Testing of Pattern-Sensitive Faults in Random-Access Memory," Technical Report CSG-56, Coordinated Science Laboratory, Aug. 1986.
2. P. Mazumder, "Networks and Embedding Aspects of Hypercellular Structures for On-Chip Parallel Processing," MSc. Thesis, Department of Computer Science, University of Alberta, 1985.
3. P. Mazumder and J. H. Patel, "Testable RAM Design," SRC Corporate Research, 1986 Annual Report.
4. P. Mazumder, "Testing and Fault-Tolerant Aspects of High-Density VLSI Memory" Ph.D. Thesis, Coordinated Science Laboratory, Aug. 1987.
5. P. Mazumder "On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional DRAMs" CRL-TR-05-88, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Apr. 1988.
6. A. Chakravarthy and P. Mazumder, "Gate Matrix Layout Techniques," CSE-TR-12-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
7. R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," CSE-TR-52-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
8. R. Venkateswaran and P. Mazumder, "On Restructuring of Hexagonal Arrays," CSE-TR-72-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
9. S. Khushro and P. Mazumder, "VLSI Cell Placement Techniques," CRL-TR-07-88, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Aug. 1988.
10. P. Mazumder, "CPLA - A Software Tool That Automatically Generates "C"-Model for PLAs," Bell Laboratories Technical Memorandum, 55612-1A-262, Aug. 1985.
11. P. Mazumder, "Placement Algorithms for CONES," Bell Laboratories Technical Memorandum, 55612-1F-210, Aug. 1986.
12. P. Mazumder, "Automatic Integrated Circuit Synthesizer: Generates PLA Layout from Behavioral Description Written in C Language," Bell Laboratories Technical Memorandum, 55612-1A-262, Aug. 1985.

Publications During 1976-1982

Published over fifteen technical papers and application ideas while working at the Bharat Electronics Ltd. during 1976-1982. Topics included:

1.	An Integrated Circuit Design for the Raster-Scan Vertical Deflection System.
2.	An Integrated Circuit Design for the Sync Processing Circuit
3.	Integrated Circuit Design for High-Gain Pre-Amplifier with Automatic Level Controller
4.	A Hybrid Circuit Design for Hearing-Aid Amplifier
5.	An Integrated Circuit Design for Quadrant Detection and Audio Amplification of Frequency-Multiplexed Voice Signal
6.	A Large-Scale Integrated Circuit Design for Stepper-Motor-Driven Analog Clock Chip
7.	Study of Failure Modes in CMOS ICs During Handling
8.	Leakage-Current-Based Fault Characterization in a Nonplanar Gas Discharge Display
9.	Design Considerations in Fabrication of Large Planar Plasma Display
10.	Application Notes on Analog and Digital Circuits

All these were published in BEL Application Notes and BEL Technical Report.

Workshop Presentations

1. P. Mazumder, "Design of a Fault-Tolerant DRAM with New On-Chip ECC," IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 1988, Springfield, Massachusetts.
2. P. Mazumder, "A Test Methodology for Electronic Neural-Network Associative Memory," International Neural Network Society First Annual Meeting, Sep. 1988, Boston, Massachusetts.
3. P. Mazumder, "Hexagonal Mesh Architecture for Routing," Office of Naval Research Workshop, Washington, Nov. 1989.
4. P. Mazumder, "Hexagonal Mesh Reconfiguration Algorithms," Office of Naval Research Workshop, Washington, Nov. 1990.
5. P. Mazumder, "Ultra-fast Circuit Design with NDR Devices," Advanced Research Project Agency: Ultra Project, Santa Fe, Oct. 1993.
6. P. Mazumder, "Ultra-fast Circuit Design with NDR Devices," Advanced Research Project Agency: Ultra Project, Santa Fe, Oct. 1994.
7. P. Mazumder, "Built-in Self-repair using Electronic Neural Networks," Advanced Research Project Agency: Neural Network Project, San Diego, Nov. 1994.

Invited Talks

Formal Talks at Industries

Quantum electronic circuit design (1996) at Intel Corporation, Santa Clara, California.
Quantum electronic circuit design (1997) at Nippon Telegraph and Telephone, Atsugi-shi, Japan.
Quantum electronic circuit design (1997) at Fraunhofer Institute, Freiburg, Germany.
Quantum electronic circuit design (1997) at Hitachi Central Research Laboratories, Kokubunji, Japan.
Quantum electronic circuit design (1997) at NEC Corporation, Tsukuba, Ibaraki, Japan.
Quantum electronic circuit design (1997) at Fujitsu, Morinosato-Wakamiya, Japan.
Quantum electronic circuit design (1994) at Texas Instruments, Dallas, Texas.
Quantum electronic circuit design (1995) at Hughes Research Laboratories, Los Angeles, California.
Memory testing (1997) at Nippon Telegraph and Telephone, Atsugi-shi, Japan.
Memory testing (1997) at Hitachi Central Research Laboratories, Kokubunji, Japan.
Memory testing (1997) at Digital Equipment Corporation, Hudson, Massachussetts
Memory testing (1987) at AT\&T Bell Laboratories, Murray Hill, New Jersey.
Memory testing (1990) at Bell Northern Research Laboratories, Ottawa, Canada
Memory testing (1997) at Fujitsu, Morinosato-Wakamiya, Japan.
Memory testing (1997) at Intel, Santa Clara, California
Embedded memory compilation (1997) at Synopsys, Palo Alto, California.
Embedded memory compilation (1997) at Neo-Magic Corporation, Santa Clara, California.
Embedded memory compilation (1997) at Ambit Design Systems, Santa Clara, California.
Memory testing (1991) at Micron Technology, Boise, Idaho.
Memory testing (1987) at MCC, Austin, Texas
Memory testing (1995) at Texas Instruments, Bangalore, India.
Memory testing (1987) at AT\&T Bell Laboratories, Homdel, New Jersey.
VLSI chip testing (1994) at ERIM Research Laboratory, Ann Arbor, Michigan.
VLSI layout techniques (1997) at Nippon Telegraph and Telephone, Atsugi-shi, Japan.
VLSI layout techniques (1989) at General Motors Research, Warren, Michigan.
VLSI layout techniques (1988) at Bell Northern Research Laboratories, Ann Arbor, Michigan.
VLSI layout techniques (1997) at Cypress Semiconductor, Santa Clara, California
VLSI layout techniques (1990) at National Semiconductor, Santa Clara, California
Built-in self-repairable IC design (1990) at Nippon Electric Company, Princeton, New Jersey.
Built-in self-repairable IC design (1989) at Bell Communications Research, Morris Town, New Jersey.
Built-in self-repairable IC design (1994) at Ford Motors Company, Dearborn, Michigan.
Built-in self-repairable IC design (1997) at Nippon Telegraph and Telephone, Atsugi-shi, Japan.
Research activities on circuit design (1996) at IBM Watson Research Center, New York.
Research activities on circuit design (1997) at Hitachi Development Laboratories, Mobarra, Japan.
Research activities on circuit design (1996) at David Sarnoff Research Center, Princeton Junction, New Jersey.
Research activities on circuit design (1997) at NEC Central Research Laboratories, Kanagawa, Japan.
Informal Presentations at Industries

Memory testing (1995) at Texas Instruments, Houston, Texas.
Embedded memory testing (1997) at Logic Vision, San Jose, California.
VLSI layout techniques (1997) at Avant, Fremont, California.
VLSI layout techniques (1996) at International Business Machine, Fishkill, New York.
Memory testing (1996) at LSI Logic,Milpitas, California.
VLSI chip layouts (1996) at Xilinx, Inc., San Jose, California.
Built-in self-repairable design (1993) at Phillips Laboratories, Kirtland, New Mexico.
Formal Talks at Universities

Multilayer VLSI routing techniques (1996) at University of California, Berkeley, California.
Memory testing (1997) at Stanford University, Palo Alto, California.
Quantum electronic circuit design (1995) at University of Illinois, Urbana-Champaign, Illinois.
Quantum electronic circuit design (1997) at University of California, Berkeley, California.
Quantum electronic circuit design (1998) at University of Notre Dame, South Bend, Indiana.
VLSI layout design (1990) at Princeton University, Princeton,New Jersey.
Memory testing (1987) at Purdue University, West Lafyette, Indiana.
Memory testing (1988) at University of Southern California, Los Angeles, California.
Built-in self-repairable IC design (1989) at University of Iowa, Iowa City, Iowa.
Memory testing (1987) at Johns Hopkins University, Baltimore, Maryland.
Memory testing (1987) at University of Minnesotta, Minneapolis, Minnesotta.
Quantum electronic circuit design (1997) at University of Tokyo, Tokyo, Japan.
Quantum electronic circuit design (1997) at Delft Technological University, Delft, Netherlands
Quantum electronic circuit design (1997) at Universidad de Las Palmas de Gran Canaria, Spain.
Memory testing and repair algorithms (1990) at Indian Institute of Technology, New Delhi, India.
Memory testing (1989) at Texas A\&M University, College Station, Texas.
Built-in self-repairable IC design (1994) at Wayne State University, Detroit, Michigan.
VLSI layout design (1995) at Indian Institute of Science, Bangalore, India.
Built-in self-repairable design (1990) at Association of Computing Machine Symposia, Ann Arbor, Michigan.
Formal Visits to University Laboratories

VLSI Design and Education Center, University of Tokyo, Tokyo, Japan (1997).
Computer Engineering Research Center, University of Texas, Austin, Texas (1995).
Nanoelectronics Laboratory, University of Texas, Dallas, Texas (1997).
Testing Laboratory, Technical University of Budapest, Budapest, Hungary (1997).
Rice University, Houston, Texas (1997).
University of North Calorina, Chapel Hill (1991).
Oxford University, Oxford, England (1992).

1.	P. Mazumder and K. Chakraborty, "Testing and Testable Design of Random-Access Memories," Kluwer Academic Publishers, 1996.
2.	P. Mazumder, "Models and Techniques for VLSI Routing," (in preparation) .
3.	P. Mazumder and E. Rudnick, "Genetic Algorithms for VLSI Design, Layout, and Test Automation," Prentice Hall, 1998.
4.	R. Rajsuman and P. Mazumder, "Semiconductor Memories: Testing and Reliability," Computer Science Press, to appear (edited version).
5.	K. Chakraborty and P. Mazumder, "Fault Tolerance and Reliability Aspects of Random-Access Memories," in preparation.

1.	K. Shahookar and P. Mazumder, "Standard Cell Placement and the Genetic Algorithm," Book chapter in "Advances in Computer-Aided Engineering Design, Vol. II," I. N. Hajj (editor), Jai Press, Greenwich, Connecticut, 1990, pp. 159-234.
2.	W. K. Fuchs, M. F. Chang, S. Y. Kuo, P. Mazumder and C. B. Stunkel, "The Impact of Parallel Architecture Granularity on Yield," Book chapter in "Designing for Yield", Moore, Strowjas and Maly (editors), Adam Hilger Publisher, 1988.
3.	P. Mazumder and J. H. Patel, "Parallel Testing of Parametric Faults in DRAM", in "Advanced Research in VLSI: Design and Applications of Very Large Scale Systems", Leighton and Allen (editors), MIT Press, 1988. (Presented at the 5-th Massachusetts Institute of Technology Conference on VLSI).
4.	P. Mazumder, "Design of a Fault-Tolerant DRAM with New On-Chip ECC," Book Chapter in "Defects and Fault Tolerance in VLSI Systems," I. Koren (editor), Plenum Press, 1989.
5.	H. Chan and P. Mazumder, "A Systolic Architecture for High-Speed Hypergraph Partitioning Using a Genetic Algorithm," Book Chapter in "Progress in Evolutionary Computation", Vol. 956, Springer-Verlag, Heildelberg, 1995, pp. 109-126.

1.	J.V. Oldfield, J.P. Gray, T.A. Kean, and R.C. Dorf, Field-Programmable Gate Arrays for Implementation and Rapid Prototyping of Digital Systems, John Wiley and Sons, Inc., New York.
2.	John Beetam, Computer Architectures, Aksen Associates Inc. Publishers, California. The Science and Technology of Microelectronic Processing, Saunders College Publishing, Pennsylvania.
3.	Dhiraj Pradhan, Fault-Tolerant System Design, Prentice Hall, New Jersey.
4.	Price, Introduction to VLSI Design, Prentice Hall, New Jersey. C.P. Ravi Kumar, Computer-Aided Design for VLSI Systems, Kluwer Academic Publishers, Massachussetts.
5.	Fu, Neural Networks in Computer Intelligence, Prentice Hall, New Jersey.
6.	P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design Applications, Prentice Hall, New Jersey.
7.	R. Karri, Automatic Synthesis of Fault-tolerant VLSI Systems, Kluwer Academic Publishers, Massachussetts.
8.	A. S. Sedra and K. C. Smith, "SPICE Simulation: Microelectronics Circuits," Prentice Hall.

1.	K. Shahookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement with Meta-Genetic Parameter Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 5, May 1990, pp. 500-511.
2.	R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 10, Oct. 1990, pp. 1096-1112.
3.	J. Yih and P. Mazumder, "A Neural Network Design for Circuit Partitioning," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 9, No. 12, Dec. 1990, pp. 1265-1271.
4.	K. Shahookar and P. Mazumder, "VLSI Cell Placement Techniques", ACM Computing Surveys, Vol. 23, No. 2, Jun. 1991, pp. 143-220 (Also, translated in Japanese and published in "bit: Computer Science '91", Kyoritsu Shuppan Co., Ltd., Tokyo).
5.	P. Mazumder, "Planar Decomposition Strategies for Quadtree Data Structure," Journal of Computer Vision, Graphics, and Image Processing, Academic Press, Jun. 1987, pp. 258-274.
6.	H. M. Chan, P. Mazumder and K. Shahookar, "Macro-Cell and Module Placement by Genetic Optimization with Bit-Map Represented Crossover Operators," Integration: An International VLSI Journal, Dec. 1991, pp. 49-77.
7.	P. Mazumder, "Layout Optimization for Yield Enhancement in On-Chip VLSI/WSI Parallel Processing," IEE Proceedings-E: Computers and Digital Techniques. Vol. 139, No. 1, Jan. 1992, pp. 21-28.
8.	S. Mohan and P. Mazumder, "WOLVERINES: A Distributed Standard Cell Placement Tool," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept. 1993, pp. 1312-1326.
9.	K. Shahookar, W. Khamisani, P. Mazumder, S.M. Reddy, "Genetic Beam Search for Gate Matrix Placement," IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2, Mar. 1994, pp. 123-128.
10.	H. Esbensen and P. Mazumder, "SAGA: Unification of Genetic Algorithm with Simulated Annealing and Its Application to Macro-Cell Placement," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
11.	R. Venkateswaran and P. Mazumder, "DA Techniques for PLD and FPGA Based Systems," Integration: An International VLSI Journal, Vol. 17, Dec. 1994, pp. 191-240.
12.	R. Venkateswaran and P. Mazumder, "Highly Parallel Grid Graph Based Routing Algorithm," IEE Proceedings-E: Computers and Digital Techniques.
13.	H. Esbensen and P. Mazumder, "Viking: Macro-cell Placement by Genetic Algorithm," IEE Proceedings-E: Computers and Digital Techniques.

1.	P. Mazumder, J. H. Patel and W. K. Fuchs, "Methodologies for Testing Embedded Content-Addressable Memories," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan. 1988, pp. 11-20.
2.	P. Mazumder, "Parallel Testing of Parametric Faults in a Three-Dimensional Dynamic Random-Access Memory," IEEE Journal of Solid-State Circuits, Vol. 23, No. 4, Aug. 1988, pp. 933-942.
3.	P. Mazumder and J. H. Patel, "Parallel Testing of Pattern-Sensitive Faults in Random-Access Memory," IEEE Transactions on Computers, Vol. 38, No 3, Mar. 1989, pp. 394-404.
4.	P. Mazumder and J. H. Patel, "An Efficient Built-In Self-Testing Algorithm for Random-Access Memory," IEEE Transactions on Industrial Electronics (Special Issue on Testing) Vol. 36, No. 3, May 1989, pp. 394-407.
5.	J. S. Yih and P. Mazumder, "Circuit Behavior Modeling and Compact Testing Performance Evaluation," IEEE Journal of Solid-State Circuits, Vol. 26, No. 1, Jan. 1991, pp. 62-65.
6.	P. Mazumder and J. H. Patel, "A Comprehensive Study of Random Testing for Embedded RAMs Using Markov Chains," Journal of Electronic Testing: Theory and Applications, Vol. 3 No. 4, Nov. 1992, 235-250.
7.	S. Mohan and P. Mazumder, "Analytical and Simulation Studies of Failure Modes in SRAM's Using High-Electron Mobility Transistors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 12, No. 12, Dec. 1993, pp. 1885-1896.
8.	P. Mazumder and J. P. Hayes, "Testing and Improving the Testability of Multimegabit Memories," IEEE Design and Test of Computers, March 1993, pp. 6-7.
9.	K. Chakraborty and P. Mazumder, "Technology and Layout Related Testing in Static Random-Access Memories," Journal of Electronic Testing: Theory and Applications, Aug. 1994.
9.	K. Chakraborty and P. Mazumder, "New March Tests for Multiport RAM Devices," Journal of Electronic Testing: Theory and Applications, Aug. 2000.

1.	P. Mazumder, J. H. Patel and J. A. Abraham, "A Reconfigurable Parallel Signature Analyzer for Concurrent Error Correction in Dynamic Random-Access Memory," IEEE Journal of Solid-State Circuits Vol. 25, No. 3, Jun. 1990, pp. 866-870.
2.	P. Mazumder and J. Yih, "Restructuring of Square Processor Arrays by Built-in Self-Repair Circuit," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 9, Sept. 1993, pp. 1255-1265.
3.	P. Mazumder, "A New On-Chip ECC Circuit for Correcting Soft Errors in DRAMs with Trench Capacitors," IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992, pp. 1623-1633.
4.	R. Venkateswaran, P. Mazumder and K. G. Shin, "On Restructuring of Hexagonal Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 12, Dec. 1992, pp. 1574-1585.
5.	P. Mazumder and J. Yih, "A New Built-in Self-Repair Approach to VLSI Memory Yield Enhancement by Using Neural-Type Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 1, Jan. 1993, pp. 124-136.
6.	P. Mazumder, "Design of a Fault-Tolerant Three-Dimensional Dynamic Random-Access Memory with On-Chip Error-Correcting Circuit," IEEE Transactions on Computers, Vol. 42, No. 12, December 1993, pp. 1453-1468.
7.	M.D. Smith and P. Mazumder, "Analysis and Design of Hopfield-type Network for Built-in Self-repair of Memories," IEEE Transactions on Computers, Vo, 45, No. 1, January 1996.
8.	P. Mazumder, "Built-In Self-Repair for WSI Hexagonal Processor Arrays," IEE Proceedings-E: Computers and Digital Techniques.

1.	P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. I. Haddad, "Digital Circuit Applications of Resonant-Tunneling Devices," Proceedings of the IEEE, Vol. 86, No. 4, April 1998, pp. 664-686. (Invited Paper)
2.	J. P. Sun, G. I. Haddad, P. Mazumder, and J. N. Schulman, "Resonant Tunneling Diodes: Models and Properties," Proceedings of the IEEE, Vol. 86, No. 4, April 1998, pp. 641-661. (Invited Paper)
3.	S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and S. Sung, "Ultrafast Pipelined Adders Using Resonant Tunneling Transistors," IEE Electronics Letters, Vol. 27, No. 10, May 1991, pp. 830-831.
4.
5.	P. Mazumder, "Evaluation of On-Chip Static Interconnection Networks," IEEE Transactions on Computers, C-36, Mar. 1987, pp. 365-369.
6.	S. Mohan, P. Mazumder, G.I. Haddad and W. L. Chen, "Pico Second Pipelined Adder Using Three-Terminal NDR Devices," IEE Proceedings-E: Computers and Digital Techniques, Vol. 141, No. 2, Mar. 1994, pp. 104-110.
7.	R. Venkateswaran and P. Mazumder, "Design of a Coprocessor for Accelerating the Maze Routing in VLSI and PCB Layouts," IEEE Transactions on VLSI Systems, Mar. 1993, Vol. 1, No. 1, pp. 1-14.
8.	S. Mohan, P. Mazumder, G. I. Haddad, R. Mains, and S. Sung, "Logic Design Based on Negative Differential Resistance Characteristics of Quantum Electronic Devices," IEE Proceedings-G: Electronic Devices, Vol. 140, No. 6, Dec. 1993, pp. 383-391.
1.	E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, "Multivalued Multiplexer Design Using Resonant Tunneling Devices and Heterojunction Bipolar Transistors," IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, August 1996, pp. 1151-1156.
2.	E. Chan, M. Bhattacharya, P. Mazumder and G.I. Haddad, "Mask Programmable Multi-Valued Logic Gate Arrays Using RTDs and HBTs," IEE Proceedings-E: Computers and Digital Techniques, Vol. 143, No. 5, October 1996, pp. 289-294.
3.	S. Mohan, J.P. Sun, P. Mazumder and G. I. Haddad, "Device and Circuit Models for Resonant Tunneling Devices for Circuit Simulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 140, No. 6, June 1995, pp. 653-662.
4.	P. Mazumder, J.P. Sun, S. Mohan and G.I. Haddad, "DC and Transient Simulation of Resonant Tunneling Devices in NDR-SPICE," Institute of Physics, No. 141, Sept. 1994, pp. 867-872
5.	G. I. Haddad and P. Mazumder, "Tunneling Decices and Applications in High Functionality/Speed Digital Circuits," Solid State Electronics, Vol. 41, No. 10, Oct. 1997, pp. 1515-1524.
6.	P. Mazumder, "An Economical Design of Programmable Seven Segments to Decimal Decoder," Electronic Design News, Apr. 1987, pp. 222-224, (Design Ideas Prize Winner).

1.	P. Mazumder, "New Switched-Mode CSMA/CD Protocol That Improves the Performance of Delay-Critical Traffic," Computer Systems - Science and Engineering.
2.	P. Mazumder, "Satellite Communications versus Submarine Cables for Long Distance Links," IETE Journal - A Special Issue on TV Communication in India, 1976 (Best Student Paper Award Winner).

1.	H. Esbensen and P. Mazumder, "A Genetic Algorithm for the Steiner Routing Problem in a Graph," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ({\em will be accepted pending some changes}).
2.	K. Chakrabaorty, A. Gupta and P. Mazumder, "BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM Compiler," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
3.	A. Gupta, K. Chakraborty and P. Mazumder, "FTROMGEN - A Fault-Tolerant Self-Repairable ROM Compiler," IEEE Transactions on VLSI Systems.
4.	R. Venkateswaran and P. Mazumder, "Parallel Algorithms for Multi-layer Detailed Routing and Steiner-tree Generation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ({\em will be accpeted pending some changes}).
5.	K. Chakraborty and P. Mazumder, "An Efficient Bus-layout based Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
6.	K. Chakraborty and P. Mazumder, "Efficient Marching Algorithms for Testing Multi-port Memories at the Board Level," IEEE Transactions on Computers.
7.	A. Gonzalez and P. Mazumder, "A Signed-Digit Adder Using RTDs and CMOS Devices," IEEE Journal of Solid-State Circuits.
8.	S. Kulkarni, P. Mazumder and G. I. Haddad, "A 32-bit RTD-based Nano-pipelined Correlator for Ultra-fast Communication Systems," IEE Proceedings-E: Computers and Digital Techniques.
9.	S. Kulkarni and P. Mazumder, "Bistable Logic Circuits using RTDs and CMOS," IEEE Transactions on Computers.
10.	M. Bhattacharya and P. Mazumder, "Analysis of HBT and RTD based Circuits," International Journal of High-Speed Electronics and Systems.
11.	P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, "Design and Simulation of Resonant-Tunneling Diode Circuits," IEEE Computer Magazine.
12.	P. Mazumder and S. Mohan, "Optimization of Multi-state Memories," IEEE Transactions on Circuits and Systems.
13.	T. Ueura and P. Mazumder, "On the Stability of RTD based Monostable-to-Bistable Transition Circuits," IEEE Transactions on Circuits and Systems.

1.	P. Mazumder, J. H. Patel and W. K. Fuchs, "Design and Algorithms for Parallel Testing of Random-Access and Content-Addressable Memory," Proc. ACM/IEEE 24th Design Automation Conference, Florida, Jun. 1987, pp. 688-694 (nominated for the Best Paper Award).
2.	P. Mazumder, "Evaluation of Three Interconnection Networks for CMOS VLSI Implementation," Proc. IEEE International Conference on Parallel Processing, St. Charles, Illinois, Aug. 1986, pp. 200-207.
3.	P. Mazumder and J. H. Patel, "Methodologies for Testing Embedded Content-Addressable Memories," Proc. IEEE 17th International Symposium on Fault-Tolerant Computing, Jul. 1987, Pittsburgh, Pennsylvania, pp. 270-275.
4.	P. Mazumder, "A Novel Universal Seven-Segment-to-Decimal Decoder," Proc. IEEE 6th Biennial University, Government and Industry Microelectronics (UGIM) Conference, Alabama, Jun. 1985.
5.	P. Mazumder and J. H. Patel, "An Efficient Built-In Self-Testing Algorithm for Random-Access Memory," Proc. IEEE International Test Conference, Sep. 1987, pp. 1072-1077.
6.	P. Mazumder and J. H. Patel, "A Novel Fault-Tolerant Design of Testable Dynamic Random-Access Memory," Proc. IEEE International Conference on Computer Design, New York, Oct. 1987, pp. 306-309.
7.	P. Mazumder, "Planar Topologies for Tree Representation," Proc. 14th Annual Conference on Numerical Mathematics and Computing Science, Winnipeg, Canada, Sep. 1984.
8.	P. Mazumder "On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional DRAMs" Proc. IEEE International Test Conference, Sep. 1988, Washington, pp. 279-288.
9.	P. Mazumder, "A New Strategy for Octtree Representation of Three-Dimensional Objects," Proc. IEEE Conference on Computer Vision and Pattern Recognition, Jun. 1988, Ann Arbor, pp. 270-275.
10.	P. Mazumder, "An Efficient Design of Embedded Memories for Random Pattern Testability," Proc. IEEE International Conference on Wafer Scale Integration, Jan. 1989, San Francisco, pp. 230-237.
11.	P. Mazumder and J. Yih, "Fault-Diagnosis and Self-Repairing of Embedded Memories by Using Electronic Neural Network," Proc. IEEE 19th Fault-Tolerant Computing Symposium, Chicago, Jun. 1989, pp. 270-277.
12	J. Yih and P. Mazumder, "A Neural Network Design for Circuit Partitioning," Proc. ACM/IEEE 26th Design-Automation Conference, Las Vegas, Jun. 1989, pp. 406-411.
13	R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," Proc. IEEE International Conference on Computer-Aided Design, Nov. 1989.
14	K. Shahookar and P. Mazumder, "A Genetic Approach to Standard Cell Placement with Meta-Genetic Parameter Optimization," Proc. IEEE European Design Automation Conference, Glasgow, England, Mar. 1990, pp. 370-378.
15.	R. B. Panwar and P. Mazumder, "A Parallel Karmarkar Algorithm Implemented on Orthogonal Tree Networks," Proc. International Parallel Processing Conference, Aug. 1990, Vol. 3., pp. 270-273.
16.	P. Mazumder and J. Yih, "Built-In Self-Repair Techniques for Yield Enhancement of Embedded Memories," Proc. IEEE International Test Conference, Sep. 1990, pp. 833-841.
17.	S. Mohan and P. Mazumder, "Wolverine: A Distributed Standard Cell Placement Tool," Proc. IEEE European Design Automation Conference, Hamburg, Germany, Sep. 1992.
18.	R. Venkateswaran, P. Mazumder and K. G. Shin, "On Restructuring of Hexagonal Processor Arrays," Intl. Conf. on Defect and Fault Tolerance in VLSI Systems, Nov 1991
19.	P. Mazumder and J. Yih, "Processor Array Self-Reconfiguration by Neural Networks," Intl. Wafer Scale Integration, Jan. 1992.
20.	S. Mohan and P. Mazumder, "Fault Characterization and Testing of GaAs Static Random-Access Memories using High-Electron Mobility Transistors," Proc. on Intl. Test Conference, Oct. 1991, Nashville, pp. 665-674.
21.	K. Shahookar, P. Mazumder and S. M. Reddy, "Gate Matrix Placement by Genetic Algorithm Combined with Beam Search," Proc. on IEEE VLSI-93, Bombay, India, Jan. 1993.
22.	P. Mazumder, "An Integrated Built-in Self-Testing and Self-Repair of Hexagonal Arrays," Proc. on International Test Conference, Baltimore, Sep. 1992.
23.	W.L. Chen, G.I. Haddad, G.O. Munns, S. Mohan and P. Mazumder, "InP-Based Quantum Effect Devices: Device Fabrication and Application in Digital Circuits," Proc. on International Electron Device and Material Symposium, Taipei, Taiwan, Nov. 1992.
24.	K. Shahookar and P. Mazumder, "Genetic Min-cut Partitioning," Proc. on VLSI 1995, New Delhi, India.
25.	R. Venkateswaran and P. Mazumder, "Highly Parallel Grid Graph Based Routing Algorithm," European Design Automation Conference, (submitted)
26.	H. Esbensen and P. Mazumder, "SAGA: Unification of Genetic Algorithm with Simulated Annealing and Its Application to Macro-Cell Placement," Proc. on IEEE VLSI-1994, Calcutta, India, Jan. 1994.
27.	H. Esbensen and P. Mazumder, "A Genetic Algorithm for the Steiner Routing Problem in a Graph," Proc. on European Design Automation Conference, Mar. 1994, Paris.
28.	E. Chan, S. Mohan, P. Mazumder and G. I. Haddad, "Multivalued Multiplexer Design Using Resonant Tunneling Devices and Heterojunction Bipolar Transistors," Proc. on Government Microciruits Application Conference, Nov. 1994, San Diego.
29.	S. Mohan, P. Mazumder and G. I. Haddad, "NDR SPICE: A Circuit Simulator for Resonant Tunneling Devices," Proc. on International Compound Semiconductors Conference, Sep. 1994, San Diego.
30.	M.D. Smith and P. Mazumder, "Analysis and Design of Hopfield-type Network for Built-in Self-repair of Memories," Proc. on Government Microciruits Application Conference, Nov. 1994, San Diego.
31.	E. Chan, P. Mazumder and G.I. Haddad, "Mask Programmable Multi-Valued Logic Gate Arrays Using RTDs and HBTs," Proc. on Intl. Electron Devices Meeting, Dec. 1994.
2.	S. Mohan, P. Mazumder and G. I. Haddad, "A New Circuit Simulator for Negative Resistance Devices," Proc. on Intl. Electron Devices Meeting, Dec. 1994.
32.	S. Kulkarni, P. Mazumder and G. I. Haddad, "A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices," International Conference on Micro-nanotechnology for Space Applications, Oct. 1995.
33.	S. Kulkarni, P. Mazumder and G. I. Haddad, "A High-speed 32-bit Parallel Correlator for Spread Spectrum Communication," Ninth International Conference on VLSI Design, Jan. 1996.
34.	H. Chan and P. Mazumder, "Genetic Algorithms and Classifier Systems," Proc. on AAAI Conference, Nov. 1994, Sydney, Australia.
35.	P. Mazumder, K. Saluja and M. Franklin, "Technology Testing of DRAMs," IEEE Memory Testing Symposium, Aug. 1995, San Jose.
36.	K. Chakraborty and P. Mazumder, "An Efficient, Bus-layout Based Method for Early Diagnosis of Bussed Driver Shorts in Printed Circuit Boards," International Conference on Computer-Aided Design, Santa Clara, California, Nov. 1996.
37.	A. Gonzalez and P. Mazumder, "High-speed Signed-digit Adder Using RTDs and MOSFETs," Proc. on Government Microcircuits Applications Conference, Las Vegas, March 1997.
38.	G.I. Haddad and P. Mazumder, "Resonant Tunneling Devices and Their Applications," Proc. on Symposium of Heterostructure Devices, Japan, Aug. 1996.
39.	P. Mazumder, "Multivalued Logic Design Using HBTs and RTDs," Proc. on Frontiers in Electronics, Tenerife, Spain, Jan. 1997.
40.	K. Chakraborty and P. Mazumder, "Efficient Marching Algorithms for Testing Multiport Memories at the Board Level," Proc. on European design and Test Conference, Paris, France, Mar. 1997.
41.	P. Mazumder, "Parallel VLSI-Routing Models for Polymorphic Processors Array," Proc. on IEEE VLSI 1997 Conference, Jan. 1997.
42.	P. Mazumder, "Ultrafast Circuits and Systems Using Quantum Devices," Proc. on Frontiers in Electronics, Tenerife, Spain, Jan. 1997.
43.	P. Mazumder and G.I. Haddad, "Digital Applications of NDR Devices," Proc. on Advanced Heterostructure Devices, Kona, Hawaii, Dec. 1996.
44.	P. Mazumder, "Genetic Algorithms for Standard and Macro-cell Placement," (invited) Proc. on INFORMS, May 1997, San Diego.
45.	P. Mazumder, "Ultrafast Circuit Design using Quantum Electronic Devices," (invited) Proc. of European Circuit Theory and Design Conference, August 1997, Budapest, Hungary.
46.	A. Gonzalez and P. Mazumder, "Multivalued Signed Digit Adder Using RTD and CMOS," Proc. of Advanced Research in VLSI Conference, Sep. 1997, Ann Arbor.
47.	P. Mazumder, M. Bhattacharya, S. Kulkarni, and A. Gonzalez, "Design and Simulation of Resonant Tunneling Diode Circuits," Proc. of IEEE VLSI 1998 Conference, Jan. 1998, Chennai, India.
48.	S. Kulkarni and P. Mazumder, "Full Adder Circuit Design Using RTDs and MOSFETs," Proc. of Govt. Microcircuit Applications Conference, Mar. 1998, Arlington.
49.	P. Mazumder, "Quantum Electronic Circuit Design," Proc. of Quantum Functional Devices, Nov. 1997, Washington D.C.
50.	P. Mazumder, "Testing and Testable Design of SRAMs and DRAMs (Invited)," Proc. on Intel Test Symposium, Mar. 1997, Santa Clara.
51.	P. Mazumder and A. Seabaugh, "Quantum Electronic Devices: Principles, fabrication and Applications," invited tutorial, GOMAC Tutorial, Mar. 1998, Arlington.
52.	M. Bhattacharya and P. Mazumder, "Noise Margin of Threshold Logic Gates for Resonant Tunneling Diodes," Proc. of 8th Great Lakes Symposium on VLSI, Lafayette, Feb. 1998.
53.	P. Mazumder, "Built-in self-repair of VLSI Chips Using Neural-type Adaptive Circuits," Invited, Proc. of SPIE (Application of Neural Networks, Fuzzy Systems, and Evolutionary Computations in Electronic CAD), July 1998.
54.	P. Mazumder, "Failure Modes in Deep-Submicron CMOS Memories," Invited for Embedded Tutorial, Proc. on VLSI Test Symposium, Monterey, Mar. 1998.
55.	N. Deb, J. Xiong, M. Bhattacharya, S. Kulkarni and P. Mazumder, "Analysis of Switching Speed and Power Dissipation of RTD-CMOS Bistable Logic Gates," Proc. of Silicon Nanoelectronics, June 1998.
56.	N. Deb and P. Mazumder, "Analysis of Failures in Deep Submicron Static RAM Cells," (submitted to the International Test Conference, Oct. 1998).
57.	G. Mittal and P. Mazumder, "Analysis of Coupling Between Bit Lines of Deep Submicron Adjoining SRAM Cells," (submitted to the International Test Conference, Oct. 1998).
58.	K. Chakrabaorty and P. Mazumder, "BISRAMGEN: A Built-In Self-Repairable SRAM and DRAM Compiler," International Test Conference, Oct. 1998.

1.	P. Mazumder and J. H. Patel, "Parallel Testing of Pattern-Sensitive Faults in Random-Access Memory," Technical Report CSG-56, Coordinated Science Laboratory, Aug. 1986.
2.	P. Mazumder, "Networks and Embedding Aspects of Hypercellular Structures for On-Chip Parallel Processing," MSc. Thesis, Department of Computer Science, University of Alberta, 1985.
3.	P. Mazumder and J. H. Patel, "Testable RAM Design," SRC Corporate Research, 1986 Annual Report.
4.	P. Mazumder, "Testing and Fault-Tolerant Aspects of High-Density VLSI Memory" Ph.D. Thesis, Coordinated Science Laboratory, Aug. 1987.
5.	P. Mazumder "On-Chip Double-Error-Correction Coding Circuit for Three-Dimensional DRAMs" CRL-TR-05-88, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Apr. 1988.
6.	A. Chakravarthy and P. Mazumder, "Gate Matrix Layout Techniques," CSE-TR-12-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
7.	R. Venkateswaran and P. Mazumder, "Hexagonal Array Machine for Multi-Layer Wire Routing," CSE-TR-52-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
8.	R. Venkateswaran and P. Mazumder, "On Restructuring of Hexagonal Arrays," CSE-TR-72-90, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, 1990.
9.	S. Khushro and P. Mazumder, "VLSI Cell Placement Techniques," CRL-TR-07-88, Technical Report, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Aug. 1988.
10.	P. Mazumder, "CPLA - A Software Tool That Automatically Generates "C"-Model for PLAs," Bell Laboratories Technical Memorandum, 55612-1A-262, Aug. 1985.
11.	P. Mazumder, "Placement Algorithms for CONES," Bell Laboratories Technical Memorandum, 55612-1F-210, Aug. 1986.
12.	P. Mazumder, "Automatic Integrated Circuit Synthesizer: Generates PLA Layout from Behavioral Description Written in C Language," Bell Laboratories Technical Memorandum, 55612-1A-262, Aug. 1985.

1.	P. Mazumder, "Design of a Fault-Tolerant DRAM with New On-Chip ECC," IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Oct. 1988, Springfield, Massachusetts.
2.	P. Mazumder, "A Test Methodology for Electronic Neural-Network Associative Memory," International Neural Network Society First Annual Meeting, Sep. 1988, Boston, Massachusetts.
3.	P. Mazumder, "Hexagonal Mesh Architecture for Routing," Office of Naval Research Workshop, Washington, Nov. 1989.
4.	P. Mazumder, "Hexagonal Mesh Reconfiguration Algorithms," Office of Naval Research Workshop, Washington, Nov. 1990.
5.	P. Mazumder, "Ultra-fast Circuit Design with NDR Devices," Advanced Research Project Agency: Ultra Project, Santa Fe, Oct. 1993.
6.	P. Mazumder, "Ultra-fast Circuit Design with NDR Devices," Advanced Research Project Agency: Ultra Project, Santa Fe, Oct. 1994.
7.	P. Mazumder, "Built-in Self-repair using Electronic Neural Networks," Advanced Research Project Agency: Neural Network Project, San Diego, Nov. 1994.