State-of-the-art technologies based on field-effect devices such as MOSFETs have, over the past several decades, met growing end user performance requirements by scaling device dimensions. The physical limits on performance improvement by scaling, using conventional device transport phenomena, will likely be reached in the early part of the next century, necessitating alternative device concepts to continue fueling the growth of the VLSI industry. As device dimensions in integrated circuits shrink to deep-submicron levels, quantum effects, such as resonant tunneling, become more prominent leading to interesting new device characteristics which can be exploited to create extremely fast and compact circuits. Several novel logic circuits using RTDs in conjunction with transistors have been proposed over the past few years. These circuits have one or more of the following advantages over conventional logic circuits: 1) reduced circuit complexity for implementing a given function, 2) low power operation, and 3) high speed operation. RTD-based circuits are usually fabricated using III-V technology which offers high performance devices such as hetero-junction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs). While such circuits demonstrate very high switching speeds, they operate at high current levels thus consuming substantially higher absolute power than equivalent CMOS circuits. Also, the packing density of III-V technology based VLSI circuits is more than an order of magnitude smaller than CMOS VLSI circuits. However, the unique NDR characteristics of RTDs coupled with their high tunneling speeds lead to very compact and fast circuit topologies. Thus it is very attractive to envision these compact, high-functionality circuits implemented in a technology such as CMOS that offers low power dissipation and very large integration levels. While co-integration of RTDs and MOSFETs is still an active area of research, we have developed new circuit topologies and system design techniques that project the performance advantages of these quantum MOS (QMOS) circuits over conventional implementations. The possible use, in the future, of these quantum MOS (QMOS) gates in deeply pipelined computing systems will result in elimination of the area, delay and power overhead of pipeline latches that limits conventional CMOS-based systems, leading to compact and fast system designs while retaining advantages of CMOS, such as low power dissipation and high packing density. In particular, communication systems and digital signal processors are expected to benefit from the gate-level pipelining approach due to their low data dependence.
Our accomplishments in QMOS circuit design are enumerated below.